From 1d0ac5b866e97ae591096d63fc6f145d127d1255 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Mon, 27 Jul 2020 19:22:31 -0400 Subject: [PATCH 1/7] drivers/video/rockchip/rk_vop.c: Use endpoint compatible string to find VOP mode The current code is using an hard coded enum and the of node reg value of endpoint to find out if the endpoint is mipi/hdmi/lvds/edp/dp. The order is different between rk3288, rk3399 vop little, rk3399 vop big. A possible solution would be to make sure that the rk3288.dtsi and rk3399.dtsi files have "expected" reg value or an other solution is to find the kind of endpoint by comparing the endpoint compatible value. This patch is implementing the more flexible second solution. Origin: http://people.hupstream.com/~rtp/pbp/20200727/dts_vop_mode.patch Signed-off-by: Arnaud Patard --- .../include/asm/arch-rockchip/vop_rk3288.h | 15 +---------- drivers/video/rockchip/rk_vop.c | 25 +++++++++++++++++-- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 872a158b714..bf19e059977 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -85,26 +85,13 @@ enum { LB_RGB_1280X8 = 0x5 }; -#if defined(CONFIG_ROCKCHIP_RK3399) enum vop_modes { VOP_MODE_EDP = 0, VOP_MODE_MIPI, VOP_MODE_HDMI, - VOP_MODE_MIPI1, - VOP_MODE_DP, - VOP_MODE_NONE, -}; -#else -enum vop_modes { - VOP_MODE_EDP = 0, - VOP_MODE_HDMI, VOP_MODE_LVDS, - VOP_MODE_MIPI, - VOP_MODE_NONE, - VOP_MODE_AUTO_DETECT, - VOP_MODE_UNKNOWN, + VOP_MODE_DP, }; -#endif /* VOP_VERSION_INFO */ #define M_FPGA_VERSION (0xffff << 16) diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 9032eb430e7..6cd4ccc97a0 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -235,12 +235,11 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) struct clk clk; enum video_log2_bpp l2bpp; ofnode remote; + const char *compat; debug("%s(%s, %lu, %s)\n", __func__, dev_read_name(dev), fbbase, ofnode_get_name(ep_node)); - vop_id = ofnode_read_s32_default(ep_node, "reg", -1); - debug("vop_id=%d\n", vop_id); ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle); if (ret) return ret; @@ -282,6 +281,28 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) if (disp) break; }; + compat = ofnode_get_property(remote, "compatible", NULL); + if (!compat) { + debug("%s(%s): Failed to find compatible property\n", + __func__, dev_read_name(dev)); + return -EINVAL; + } + if (strstr(compat, "edp")) { + vop_id = VOP_MODE_EDP; + } else if (strstr(compat, "mipi")) { + vop_id = VOP_MODE_MIPI; + } else if (strstr(compat, "hdmi")) { + vop_id = VOP_MODE_HDMI; + } else if (strstr(compat, "cdn-dp")) { + vop_id = VOP_MODE_DP; + } else if (strstr(compat, "lvds")) { + vop_id = VOP_MODE_LVDS; + } else { + debug("%s(%s): Failed to find vop mode for %s\n", + __func__, dev_read_name(dev), compat); + return -EINVAL; + } + debug("vop_id=%d\n", vop_id); disp_uc_plat = dev_get_uclass_platdata(disp); debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); -- 2.25.4 From 39ea1f49c03ef6eaa4305f8d1bcea46c08d8a1a4 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Mon, 27 Jul 2020 19:23:24 -0400 Subject: [PATCH 2/7] drivers/video/rockchip/rk_edp.c: Add rk3399 support According to linux commit "drm/rockchip: analogix_dp: add rk3399 eDP support" (82872e42bb1501dd9e60ca430f4bae45a469aa64), rk3288 and rk3399 eDP IPs are nearly the same, the difference is in the grf register (SOC_CON6 versus SOC_CON20). So, change the code to use the right register on each IP. The clocks don't seem to be the same, the eDP clock is not at index 1 on rk3399, so don't try changing the clock at index 1 to rate 0 on rk3399. Origin: http://people.hupstream.com/~rtp/pbp/20200727/rk_edp_rk3399.patch Signed-off-by: Arnaud Patard --- .../include/asm/arch-rockchip/edp_rk3288.h | 5 +- drivers/video/rockchip/rk_edp.c | 85 ++++++++++++++----- 2 files changed, 68 insertions(+), 22 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h index 105a335daba..c861f0eab18 100644 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -232,8 +232,9 @@ check_member(rk3288_edp, pll_reg_5, 0xa00); #define PD_CH0 (0x1 << 0) /* pll_reg_1 */ -#define REF_CLK_24M (0x1 << 1) -#define REF_CLK_27M (0x0 << 1) +#define REF_CLK_24M (0x1 << 0) +#define REF_CLK_27M (0x0 << 0) +#define REF_CLK_MASK (0x1 << 0) /* line_map */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 000bd481408..1b2f5f706d5 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -17,11 +17,10 @@ #include #include #include +#include #include #include -#include -#include -#include +#include #define MAX_CR_LOOP 5 #define MAX_EQ_LOOP 5 @@ -37,18 +36,42 @@ static const char * const pre_emph_names[] = { #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 +#define RK3288_GRF_SOC_CON6 0x025c +#define RK3288_GRF_SOC_CON12 0x0274 +#define RK3399_GRF_SOC_CON20 0x6250 +#define RK3399_GRF_SOC_CON25 0x6264 + +enum rockchip_dp_types { + RK3288_DP = 0, + RK3399_EDP +}; + +struct rockchip_dp_data { + unsigned long reg_vop_big_little; + unsigned long reg_vop_big_little_sel; + unsigned long reg_ref_clk_sel; + unsigned long ref_clk_sel_bit; + enum rockchip_dp_types chip_type; +}; + struct rk_edp_priv { struct rk3288_edp *regs; - struct rk3288_grf *grf; + void *grf; struct udevice *panel; struct link_train link_train; u8 train_set[4]; }; -static void rk_edp_init_refclk(struct rk3288_edp *regs) +static void rk_edp_init_refclk(struct rk3288_edp *regs, enum rockchip_dp_types chip_type) { writel(SEL_24M, ®s->analog_ctl_2); - writel(REF_CLK_24M, ®s->pll_reg_1); + u32 reg; + + reg = REF_CLK_24M; + if (chip_type == RK3288_DP) + reg ^= REF_CLK_MASK; + writel(reg, ®s->pll_reg_1); + writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US | V2L_CUR_SEL_1MA, ®s->pll_reg_2); @@ -1023,6 +1046,8 @@ static int rk_edp_probe(struct udevice *dev) struct display_plat *uc_plat = dev_get_uclass_platdata(dev); struct rk_edp_priv *priv = dev_get_priv(dev); struct rk3288_edp *regs = priv->regs; + struct rockchip_dp_data *edp_data = (struct rockchip_dp_data *)dev_get_driver_data(dev); + struct clk clk; int ret; @@ -1037,16 +1062,17 @@ static int rk_edp_probe(struct udevice *dev) int vop_id = uc_plat->source_id; debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id); - ret = clk_get_by_index(dev, 1, &clk); - if (ret >= 0) { - ret = clk_set_rate(&clk, 0); - clk_free(&clk); - } - if (ret) { - debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret); - return ret; + if (edp_data->chip_type == RK3288_DP) { + ret = clk_get_by_index(dev, 1, &clk); + if (ret >= 0) { + ret = clk_set_rate(&clk, 0); + clk_free(&clk); + } + if (ret) { + debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret); + return ret; + } } - ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); if (ret >= 0) { ret = clk_set_rate(&clk, 192000000); @@ -1059,15 +1085,17 @@ static int rk_edp_probe(struct udevice *dev) } /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */ - rk_setreg(&priv->grf->soc_con12, 1 << 4); + rk_setreg(priv->grf + edp_data->reg_ref_clk_sel, + edp_data->ref_clk_sel_bit); /* select epd signal from vop0 or vop1 */ - rk_clrsetreg(&priv->grf->soc_con6, (1 << 5), - (vop_id == 1) ? (1 << 5) : (0 << 5)); + rk_clrsetreg(priv->grf + edp_data->reg_vop_big_little, + edp_data->reg_vop_big_little_sel, + (vop_id == 1) ? edp_data->reg_vop_big_little_sel : 0); rockchip_edp_wait_hpd(priv); - rk_edp_init_refclk(regs); + rk_edp_init_refclk(regs, edp_data->chip_type); rk_edp_init_interrupt(regs); rk_edp_enable_sw_function(regs); ret = rk_edp_init_analog_func(regs); @@ -1083,8 +1111,25 @@ static const struct dm_display_ops dp_rockchip_ops = { .enable = rk_edp_enable, }; +static const struct rockchip_dp_data rk3399_edp = { + .reg_vop_big_little = RK3399_GRF_SOC_CON20, + .reg_vop_big_little_sel = BIT(5), + .reg_ref_clk_sel = RK3399_GRF_SOC_CON25, + .ref_clk_sel_bit = BIT(11), + .chip_type = RK3399_EDP, +}; + +static const struct rockchip_dp_data rk3288_dp = { + .reg_vop_big_little = RK3288_GRF_SOC_CON6, + .reg_vop_big_little_sel = BIT(5), + .reg_ref_clk_sel = RK3288_GRF_SOC_CON12, + .ref_clk_sel_bit = BIT(4), + .chip_type = RK3288_DP, +}; + static const struct udevice_id rockchip_dp_ids[] = { - { .compatible = "rockchip,rk3288-edp" }, + { .compatible = "rockchip,rk3288-edp", .data = (ulong)&rk3288_dp }, + { .compatible = "rockchip,rk3399-edp", .data = (ulong)&rk3399_edp }, { } }; -- 2.25.4 From 3f9f4ba5476972011794e7023dd0f5a2db1abede Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Mon, 27 Jul 2020 19:23:27 -0400 Subject: [PATCH 3/7] rk3399-pinebook-pro-u-boot.dtsi: Enable edp - uboot rockchip edp code is looking for a rockchip,panel property for the edp dts node, so add it. Origin: http://people.hupstream.com/~rtp/pbp/20200727/update_pinebook_pro_uboot_dtsi.patch Signed-off-by: Arnaud Patard --- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index 1a2e24d3ef5..f0b58909a4b 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -41,3 +41,7 @@ &vdd_log { regulator-init-microvolt = <950000>; }; + +&edp { + rockchip,panel = <&edp_panel>; +}; -- 2.25.4 From 9ae9e65232c4f810567bced0f04111dbadfad287 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Mon, 27 Jul 2020 19:23:30 -0400 Subject: [PATCH 4/7] PBP: Fix panel reset On warm reset, the pinebook pro panel is not working correctly. The issue is not yet debugged so, for now, this hack seems to be enough. It toggles the GPIO1_C6 gpio [ LCDVCC_EN signal in the schematics ] used by the vcc3v3_panel regulator. There's no gpio_request, since the gpio is already in use at this stage, so it can only fail. Origin: http://people.hupstream.com/~rtp/pbp/20200727/hack-reset.patch --- board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c index 516292aaa59..6b8376d6cd9 100644 --- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c +++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c @@ -7,9 +7,12 @@ #include #include #include +#include +#include #include #include #include +#include #include #include #include @@ -59,6 +62,7 @@ int misc_init_r(void) const u32 cpuid_length = 0x10; u8 cpuid[cpuid_length]; int ret; + unsigned int gpio; setup_iodomain(); @@ -70,6 +74,11 @@ int misc_init_r(void) if (ret) return ret; + gpio_lookup_name("B22", NULL, NULL, &gpio); + gpio_direction_output(gpio, 0); + mdelay(500); + gpio_direction_output(gpio, 1); + return ret; } #endif -- 2.25.4 From 3a46df81e1b59695e44cae08004ce77b70fbdd46 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Mon, 27 Jul 2020 19:23:42 -0400 Subject: [PATCH 5/7] SPL malloc() before relocation used 0x22d0 bytes (8 KB) spl_init Trying to boot from BOOTROM Returning to boot ROM... spl_early_init pmic@1b: ret=-6 i2c@ff3c0000: ret=-6 dm_scan_fdt() failed: -6 dm_extended_scan_dt() failed: -6 dm_init_and_scan() returned error -6 spl_early_init() failed: -6 Origin: http://people.hupstream.com/~rtp/pbp/20200727/pmic-dm-reloc.patch --- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index f0b58909a4b..0f8879c4ca3 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -20,9 +20,9 @@ u-boot,dm-pre-reloc; }; -&rk808 { +/*&rk808 { u-boot,dm-pre-reloc; -}; +};*/ &sdhci { max-frequency = <25000000>; -- 2.25.4 From 51533b5a9b9963c05c2ddd21aee99b08adb8b48a Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Mon, 27 Jul 2020 19:23:49 -0400 Subject: [PATCH 6/7] rk3399-pinebook-pro-u-boot.dts: "disable_cdp_dp.patch" Origin: http://people.hupstream.com/~rtp/pbp/20200727/disable_cdp_dp.patch --- arch/arm/dts/rk3399-pinebook-pro.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts index 294d21bf45f..4e2dd140841 100644 --- a/arch/arm/dts/rk3399-pinebook-pro.dts +++ b/arch/arm/dts/rk3399-pinebook-pro.dts @@ -372,9 +372,9 @@ }; }; -&cdn_dp { +/*&cdn_dp { status = "okay"; -}; +};*/ &cpu_b0 { cpu-supply = <&vdd_cpu_b>; -- 2.25.4 From cf24efba24a7aae0596be03487f77fe25238381e Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Mon, 27 Jul 2020 19:23:52 -0400 Subject: [PATCH 7/7] drivers/video/rockchip/rk_vop.c: Reserve efi fb memory When booting with EFI and graphics, the memory used for framebuffer has to be reserved, otherwise it may leads to kernel memory overwrite. Origin: http://people.hupstream.com/~rtp/pbp/20200727/rk_vop_reserve_fb_memory.patch Signed-off-by: Arnaud Patard --- drivers/video/rockchip/rk_vop.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 6cd4ccc97a0..fe5ff977d7e 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include #include @@ -394,6 +396,13 @@ int rk_vop_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) return 0; + plat->base = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - plat->size; + +#ifdef CONFIG_EFI_LOADER + debug("Adding to EFI map %d @ %lx\n", plat->size, plat->base); + efi_add_memory_map(plat->base, plat->size, EFI_RESERVED_MEMORY_TYPE); +#endif + priv->regs = (struct rk3288_vop *)dev_read_addr(dev); /* -- 2.25.4