From c586a5ffb8c85f30546340e323e9eeda8d3ae3ae Mon Sep 17 00:00:00 2001 From: Samuel Dionne-Riel Date: Sun, 26 Jul 2020 20:43:31 -0400 Subject: [PATCH] linux_pinebookpro_latest: workaround for display init And follow latest from Nixpkgs --- ...Read-initial-hardware-state-at-reque.patch | 51 + kernel/latest/default.nix | 98 +- kernel/latest/pinebookpro-5.7.patch | 6343 +++++++++++++++++ 3 files changed, 6427 insertions(+), 65 deletions(-) create mode 100644 kernel/latest/0001-HACK-Revert-pwm-Read-initial-hardware-state-at-reque.patch create mode 100644 kernel/latest/pinebookpro-5.7.patch diff --git a/kernel/latest/0001-HACK-Revert-pwm-Read-initial-hardware-state-at-reque.patch b/kernel/latest/0001-HACK-Revert-pwm-Read-initial-hardware-state-at-reque.patch new file mode 100644 index 0000000..667b998 --- /dev/null +++ b/kernel/latest/0001-HACK-Revert-pwm-Read-initial-hardware-state-at-reque.patch @@ -0,0 +1,51 @@ +From 84517c6e2aac4fb32c8b02b5713297b37c140b4f Mon Sep 17 00:00:00 2001 +From: Samuel Dionne-Riel +Date: Sun, 26 Jul 2020 19:31:59 -0400 +Subject: [PATCH] [HACK] Revert "pwm: Read initial hardware state at request + time" + +This is a WORKAROUND for the issue where recent kernels will hang at +display initialization with recent kernels. + +This reverts commit cfc4c189bc70b1acc17e6f1abf1dc1c0ae890bd8. +--- + drivers/pwm/core.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c +index 004b2ea9b5fd..245e2fcfc779 100644 +--- a/drivers/pwm/core.c ++++ b/drivers/pwm/core.c +@@ -117,14 +117,6 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label) + } + } + +- if (pwm->chip->ops->get_state) { +- pwm->chip->ops->get_state(pwm->chip, pwm, &pwm->state); +- trace_pwm_get(pwm, &pwm->state); +- +- if (IS_ENABLED(CONFIG_PWM_DEBUG)) +- pwm->last = pwm->state; +- } +- + set_bit(PWMF_REQUESTED, &pwm->flags); + pwm->label = label; + +@@ -305,6 +297,14 @@ int pwmchip_add_with_polarity(struct pwm_chip *chip, + pwm->hwpwm = i; + pwm->state.polarity = polarity; + ++ if (pwm->chip->ops->get_state) { ++ pwm->chip->ops->get_state(pwm->chip, pwm, &pwm->state); ++ trace_pwm_get(pwm, &pwm->state); ++ ++ if (IS_ENABLED(CONFIG_PWM_DEBUG)) ++ pwm->last = pwm->state; ++ } ++ + radix_tree_insert(&pwm_tree, pwm->pwm, pwm); + } + +-- +2.25.4 + diff --git a/kernel/latest/default.nix b/kernel/latest/default.nix index b53ecae..efe1f1d 100644 --- a/kernel/latest/default.nix +++ b/kernel/latest/default.nix @@ -1,71 +1,39 @@ -{ stdenv -, pkgs -, lib -, kernelPatches -, buildPackages -, fetchFromGitLab -, perl -, buildLinux -, modDirVersionArg ? null -, ... } @ args: - -let - inherit (stdenv.lib) - concatStrings - intersperse - take - splitString - optionalString - ; - version = "5.7"; - additionalConfig = { - name = "pinebookpro-config-fixes"; - patch = null; - extraConfig = '' - PCIE_ROCKCHIP y - PCIE_ROCKCHIP_HOST y - PCIE_DW_PLAT y - PCIE_DW_PLAT_HOST y - PHY_ROCKCHIP_PCIE y - PHY_ROCKCHIP_INNO_HDMI y - PHY_ROCKCHIP_DP y - ROCKCHIP_MBOX y - STAGING_MEDIA y - VIDEO_HANTRO y - VIDEO_HANTRO_ROCKCHIP y - USB_DWC2_PCI y - ROCKCHIP_LVDS y - ROCKCHIP_RGB y - ''; - }; -in - -buildLinux (args // { - inherit version; +{ pkgs, lib, linux_5_7, kernelPatches, ... } @ args: +linux_5_7.override({ kernelPatches = lib.lists.unique (kernelPatches ++ [ pkgs.kernelPatches.bridge_stp_helper pkgs.kernelPatches.request_key_helper pkgs.kernelPatches.export_kernel_fpu_functions."5.3" - additionalConfig + { + name = "pinebookpro-5.7.patch"; + patch = ./pinebookpro-5.7.patch; + } + { + name = "0001-HACK-Revert-pwm-Read-initial-hardware-state-at-reque.patch"; + patch = ./0001-HACK-Revert-pwm-Read-initial-hardware-state-at-reque.patch; + } + { + name = "pinebookpro-config-fixes"; + patch = null; + extraConfig = '' + PCIE_ROCKCHIP y + PCIE_ROCKCHIP_HOST y + PCIE_DW_PLAT y + PCIE_DW_PLAT_HOST y + PHY_ROCKCHIP_PCIE y + PHY_ROCKCHIP_INNO_HDMI y + PHY_ROCKCHIP_DP y + ROCKCHIP_MBOX y + STAGING_MEDIA y + VIDEO_HANTRO y + VIDEO_HANTRO_ROCKCHIP y + USB_DWC2_PCI y + ROCKCHIP_LVDS y + ROCKCHIP_RGB y + ''; + } ]); - - # modDirVersion needs to be x.y.z, will automatically add .0 if needed - modDirVersion = if (modDirVersionArg == null) then concatStrings (intersperse "." (take 3 (splitString "." "${version}.0"))) else modDirVersionArg; - - # branchVersion needs to be x.y - extraMeta.branch = concatStrings (intersperse "." (take 2 (splitString "." version))); - - src = fetchFromGitLab { - domain = "gitlab.manjaro.org"; - owner = "tsys"; - repo = "linux-pinebook-pro"; - rev = "a8f4db8a726e5e4552e61333dcd9ea1ff35f39f9"; - sha256 = "1vbach0y28c29hjjx4sc9hda4jxyqfhv4wlip3ky93vf4gxm2fij"; - }; - - postInstall = (optionalString (args ? postInstall) args.postInstall) + '' - mkdir -p "$out/nix-support" - cp -v "$buildRoot/.config" "$out/nix-support/build.config" - ''; -} // (args.argsOverride or {})) +}) +// +(args.argsOverride or {}) diff --git a/kernel/latest/pinebookpro-5.7.patch b/kernel/latest/pinebookpro-5.7.patch new file mode 100644 index 0000000..c3f922d --- /dev/null +++ b/kernel/latest/pinebookpro-5.7.patch @@ -0,0 +1,6343 @@ +From bc5ae50dbbce7549ad98ebcc20707e6531b6aee7 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 13:58:31 +0200 +Subject: [PATCH 01/25] power: supply: Add support for CellWise cw2015 fuel + gauge + +Drop this once the mainline driver lands + +Signed-off-by: Tobias Schramm +--- + .../bindings/power/supply/cw2015_battery.txt | 40 + + .../bindings/power/supply/cw2015_battery.yaml | 82 ++ + .../devicetree/bindings/vendor-prefixes.yaml | 2 + + MAINTAINERS | 6 + + drivers/power/supply/Kconfig | 11 + + drivers/power/supply/Makefile | 1 + + drivers/power/supply/cw2015_battery.c | 750 ++++++++++++++++++ + 7 files changed, 892 insertions(+) + create mode 100644 Documentation/devicetree/bindings/power/supply/cw2015_battery.txt + create mode 100644 Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml + create mode 100644 drivers/power/supply/cw2015_battery.c + +diff --git a/Documentation/devicetree/bindings/power/supply/cw2015_battery.txt b/Documentation/devicetree/bindings/power/supply/cw2015_battery.txt +new file mode 100644 +index 000000000000..6128dbbccb82 +--- /dev/null ++++ b/Documentation/devicetree/bindings/power/supply/cw2015_battery.txt +@@ -0,0 +1,40 @@ ++cw2015_battery ++~~~~~~~~~~~~~~~~ ++ ++The cellwise CW2015 is a shuntless single cell battery fuel gauge. ++ ++Required properties : ++ - compatible : "cellwise,cw2015" ++ - reg: i2c address ++ ++Optional properties : ++ - cellwise,bat-config-info : 64 byte binary battery info blob ++ - cellwise,monitor-interval-ms : Measurement interval in milliseconds ++ - power-supplies: List of phandles from chargers ++ - monitored-battery: phandle of a simpl-battery ++ ++Example: ++ bat: battery { ++ compatible = "simple-battery"; ++ voltage-min-design-microvolt = <3000000>; ++ voltage-max-design-microvolt = <4350000>; ++ charge-full-design-microamp-hours = <9800000>; ++ } ++ ++ cw2015@62 { ++ compatible = "cellwise,cw201x"; ++ reg = <0x62>; ++ cellwise,bat-config-info = /bits/ 8 < ++ 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 ++ 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 ++ 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 ++ 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 ++ 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 ++ 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D ++ 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB ++ 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 ++ >; ++ cellwise,monitor-interval-ms = <5000>; ++ power-supplies = <&mains_charger>, <&usb_charger>; ++ monitored-battery = <&bat>; ++ } +diff --git a/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml b/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml +new file mode 100644 +index 000000000000..4a265d4234b9 +--- /dev/null ++++ b/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml +@@ -0,0 +1,82 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/power/supply/cw2015_battery.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Battery driver for CW2015 shuntless fuel gauge by CellWise. ++ ++maintainers: ++ - Tobias Schramm ++ ++description: | ++ The driver can utilize information from a simple-battery linked via a ++ phandle in monitored-battery. If specified the driver uses the ++ charge-full-design-microamp-hours property of the battery. ++ ++properties: ++ compatible: ++ const: cellwise,cw2015 ++ ++ reg: ++ maxItems: 1 ++ ++ cellwise,battery-profile: ++ description: | ++ This property specifies characteristics of the battery used. The format ++ of this binary blob is kept secret by CellWise. The only way to obtain ++ it is to mail two batteries to a test facility of CellWise and receive ++ back a test report with the binary blob. ++ allOf: ++ - $ref: /schemas/types.yaml#definitions/uint8-array ++ items: ++ - minItems: 64 ++ maxItems: 64 ++ ++ cellwise,monitor-interval-ms: ++ description: ++ Specifies the interval in milliseconds gauge values are polled at ++ minimum: 250 ++ ++ power-supplies: ++ description: ++ Specifies supplies used for charging the battery connected to this gauge ++ allOf: ++ - $ref: /schemas/types.yaml#/definitions/phandle-array ++ - minItems: 1 ++ maxItems: 8 # Should be enough ++ ++ monitored-battery: ++ description: ++ Specifies the phandle of a simple-battery connected to this gauge ++ $ref: /schemas/types.yaml#/definitions/phandle ++ ++required: ++ - compatible ++ - reg ++ ++examples: ++ - | ++ i2c { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cw2015@62 { ++ compatible = "cellwise,cw201x"; ++ reg = <0x62>; ++ cellwise,battery-profile = /bits/ 8 < ++ 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 ++ 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 ++ 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 ++ 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 ++ 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 ++ 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D ++ 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB ++ 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 ++ >; ++ cellwise,monitor-interval-ms = <5000>; ++ monitored-battery = <&bat>; ++ power-supplies = <&mains_charger>, <&usb_charger>; ++ }; ++ }; ++ +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index d3891386d671..58cf4e8b8d56 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -179,6 +179,8 @@ patternProperties: + description: Cadence Design Systems Inc. + "^cdtech,.*": + description: CDTech(H.K.) Electronics Limited ++ "^cellwise,.*": ++ description: CellWise Microelectronics Co., Ltd + "^ceva,.*": + description: Ceva, Inc. + "^chipidea,.*": +diff --git a/MAINTAINERS b/MAINTAINERS +index 50659d76976b..744fe0f31bbc 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -3933,6 +3933,12 @@ F: arch/powerpc/include/uapi/asm/spu*.h + F: arch/powerpc/oprofile/*cell* + F: arch/powerpc/platforms/cell/ + ++CELLWISE CW2015 BATTERY DRIVER ++M: Tobias Schrammm ++S: Maintained ++F: Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml ++F: drivers/power/supply/cw2015_battery.c ++ + CEPH COMMON CODE (LIBCEPH) + M: Ilya Dryomov + M: Jeff Layton +diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig +index f3424fdce341..7953e6c92521 100644 +--- a/drivers/power/supply/Kconfig ++++ b/drivers/power/supply/Kconfig +@@ -116,6 +116,17 @@ config BATTERY_CPCAP + Say Y here to enable support for battery on Motorola + phones and tablets such as droid 4. + ++config BATTERY_CW2015 ++ tristate "CW2015 Battery driver" ++ depends on I2C ++ select REGMAP_I2C ++ help ++ Say Y here to enable support for the cellwise cw2015 ++ battery fuel gauge (used in the Pinebook Pro & others) ++ ++ This driver can also be built as a module. If so, the module will be ++ called cw2015_battery. ++ + config BATTERY_DS2760 + tristate "DS2760 battery driver (HP iPAQ & others)" + depends on W1 +diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile +index 6c7da920ea83..69727a10e835 100644 +--- a/drivers/power/supply/Makefile ++++ b/drivers/power/supply/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_BATTERY_ACT8945A) += act8945a_charger.o + obj-$(CONFIG_BATTERY_AXP20X) += axp20x_battery.o + obj-$(CONFIG_CHARGER_AXP20X) += axp20x_ac_power.o + obj-$(CONFIG_BATTERY_CPCAP) += cpcap-battery.o ++obj-$(CONFIG_BATTERY_CW2015) += cw2015_battery.o + obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o + obj-$(CONFIG_BATTERY_DS2780) += ds2780_battery.o + obj-$(CONFIG_BATTERY_DS2781) += ds2781_battery.o +diff --git a/drivers/power/supply/cw2015_battery.c b/drivers/power/supply/cw2015_battery.c +new file mode 100644 +index 000000000000..ccfc9e78beeb +--- /dev/null ++++ b/drivers/power/supply/cw2015_battery.c +@@ -0,0 +1,750 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Fuel gauge driver for CellWise 2013 / 2015 ++ * ++ * Copyright (C) 2012, RockChip ++ * Copyright (C) 2020, Tobias Schramm ++ * ++ * Authors: xuhuicong ++ * Authors: Tobias Schramm ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CW2015_SIZE_BATINFO 64 ++ ++#define CW2015_RESET_TRIES 5 ++ ++#define CW2015_REG_VERSION 0x00 ++#define CW2015_REG_VCELL 0x02 ++#define CW2015_REG_SOC 0x04 ++#define CW2015_REG_RRT_ALERT 0x06 ++#define CW2015_REG_CONFIG 0x08 ++#define CW2015_REG_MODE 0x0A ++#define CW2015_REG_BATINFO 0x10 ++ ++#define CW2015_MODE_SLEEP_MASK GENMASK(7, 6) ++#define CW2015_MODE_SLEEP (0x03 << 6) ++#define CW2015_MODE_NORMAL (0x00 << 6) ++#define CW2015_MODE_QUICK_START (0x03 << 4) ++#define CW2015_MODE_RESTART (0x0f << 0) ++ ++#define CW2015_CONFIG_UPDATE_FLG (0x01 << 1) ++#define CW2015_ATHD(x) ((x) << 3) ++#define CW2015_MASK_ATHD GENMASK(7, 3) ++#define CW2015_MASK_SOC GENMASK(12, 0) ++ ++/* reset gauge of no valid state of charge could be polled for 40s */ ++#define CW2015_BAT_SOC_ERROR_MS (40 * MSEC_PER_SEC) ++/* reset gauge if state of charge stuck for half an hour during charging */ ++#define CW2015_BAT_CHARGING_STUCK_MS (1800 * MSEC_PER_SEC) ++ ++/* poll interval from CellWise GPL Android driver example */ ++#define CW2015_DEFAULT_POLL_INTERVAL_MS 8000 ++ ++#define CW2015_AVERAGING_SAMPLES 3 ++ ++struct cw_battery { ++ struct device *dev; ++ struct workqueue_struct *battery_workqueue; ++ struct delayed_work battery_delay_work; ++ struct regmap *regmap; ++ struct power_supply *rk_bat; ++ struct power_supply_battery_info battery; ++ u8 *bat_profile; ++ ++ bool charger_attached; ++ bool battery_changed; ++ ++ int soc; ++ int voltage_mv; ++ int status; ++ int time_to_empty; ++ int charge_count; ++ ++ u32 poll_interval_ms; ++ u8 alert_level; ++ ++ unsigned int read_errors; ++ unsigned int charge_stuck_cnt; ++}; ++ ++static int cw_read_word(struct cw_battery *cw_bat, u8 reg, u16 *val) ++{ ++ __be16 value; ++ int ret; ++ ++ ret = regmap_bulk_read(cw_bat->regmap, reg, &value, sizeof(value)); ++ if (ret) ++ return ret; ++ ++ *val = be16_to_cpu(value); ++ return 0; ++} ++ ++int cw_update_profile(struct cw_battery *cw_bat) ++{ ++ int ret; ++ unsigned int reg_val; ++ u8 reset_val; ++ ++ /* make sure gauge is not in sleep mode */ ++ ret = regmap_read(cw_bat->regmap, CW2015_REG_MODE, ®_val); ++ if (ret) ++ return ret; ++ ++ reset_val = reg_val; ++ if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) { ++ dev_err(cw_bat->dev, ++ "Gauge is in sleep mode, can't update battery info\n"); ++ return -EINVAL; ++ } ++ ++ /* write new battery info */ ++ ret = regmap_raw_write(cw_bat->regmap, CW2015_REG_BATINFO, ++ cw_bat->bat_profile, ++ CW2015_SIZE_BATINFO); ++ if (ret) ++ return ret; ++ ++ /* set config update flag */ ++ reg_val |= CW2015_CONFIG_UPDATE_FLG; ++ reg_val &= ~CW2015_MASK_ATHD; ++ reg_val |= CW2015_ATHD(cw_bat->alert_level); ++ ret = regmap_write(cw_bat->regmap, CW2015_REG_CONFIG, reg_val); ++ if (ret) ++ return ret; ++ ++ /* reset gauge to apply new battery profile */ ++ reset_val &= ~CW2015_MODE_RESTART; ++ reg_val = reset_val | CW2015_MODE_RESTART; ++ ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reg_val); ++ if (ret) ++ return ret; ++ ++ /* wait for gauge to reset */ ++ msleep(20); ++ ++ /* clear reset flag */ ++ ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); ++ if (ret) ++ return ret; ++ ++ /* wait for gauge to become ready */ ++ ret = regmap_read_poll_timeout(cw_bat->regmap, CW2015_REG_SOC, ++ reg_val, reg_val <= 100, ++ 10 * USEC_PER_MSEC, 10 * USEC_PER_SEC); ++ if (ret) ++ dev_err(cw_bat->dev, ++ "Gauge did not become ready after profile upload\n"); ++ else ++ dev_dbg(cw_bat->dev, "Battery profile updated\n"); ++ ++ return ret; ++} ++ ++static int cw_init(struct cw_battery *cw_bat) ++{ ++ int ret; ++ unsigned int reg_val = CW2015_MODE_SLEEP; ++ ++ if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) { ++ reg_val = CW2015_MODE_NORMAL; ++ ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reg_val); ++ if (ret) ++ return ret; ++ } ++ ++ ret = regmap_read(cw_bat->regmap, CW2015_REG_CONFIG, ®_val); ++ if (ret) ++ return ret; ++ ++ if ((reg_val & CW2015_MASK_ATHD) != CW2015_ATHD(cw_bat->alert_level)) { ++ dev_dbg(cw_bat->dev, "Setting new alert level\n"); ++ reg_val &= ~CW2015_MASK_ATHD; ++ reg_val |= ~CW2015_ATHD(cw_bat->alert_level); ++ ret = regmap_write(cw_bat->regmap, CW2015_REG_CONFIG, reg_val); ++ if (ret) ++ return ret; ++ } ++ ++ ret = regmap_read(cw_bat->regmap, CW2015_REG_CONFIG, ®_val); ++ if (ret) ++ return ret; ++ ++ if (!(reg_val & CW2015_CONFIG_UPDATE_FLG)) { ++ dev_dbg(cw_bat->dev, ++ "Battery profile not present, uploading battery profile\n"); ++ if (cw_bat->bat_profile) { ++ ret = cw_update_profile(cw_bat); ++ if (ret) { ++ dev_err(cw_bat->dev, ++ "Failed to upload battery profile\n"); ++ return ret; ++ } ++ } else { ++ dev_warn(cw_bat->dev, ++ "No profile specified, continuing without profile\n"); ++ } ++ } else if (cw_bat->bat_profile) { ++ u8 bat_info[CW2015_SIZE_BATINFO]; ++ ++ ret = regmap_raw_read(cw_bat->regmap, CW2015_REG_BATINFO, ++ bat_info, CW2015_SIZE_BATINFO); ++ if (ret) { ++ dev_err(cw_bat->dev, ++ "Failed to read stored battery profile\n"); ++ return ret; ++ } ++ ++ if (memcmp(bat_info, cw_bat->bat_profile, CW2015_SIZE_BATINFO)) { ++ dev_warn(cw_bat->dev, "Replacing stored battery profile\n"); ++ ret = cw_update_profile(cw_bat); ++ if (ret) ++ return ret; ++ } ++ } else { ++ dev_warn(cw_bat->dev, ++ "Can't check current battery profile, no profile provided\n"); ++ } ++ ++ dev_dbg(cw_bat->dev, "Battery profile configured\n"); ++ return 0; ++} ++ ++static int cw_power_on_reset(struct cw_battery *cw_bat) ++{ ++ int ret; ++ unsigned char reset_val; ++ ++ reset_val = CW2015_MODE_SLEEP; ++ ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); ++ if (ret) ++ return ret; ++ ++ /* wait for gauge to enter sleep */ ++ msleep(20); ++ ++ reset_val = CW2015_MODE_NORMAL; ++ ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); ++ if (ret) ++ return ret; ++ ++ ret = cw_init(cw_bat); ++ if (ret) ++ return ret; ++ return 0; ++} ++ ++#define HYSTERESIS(current, previous, up, down) \ ++ (((current) < (previous) + (up)) && ((current) > (previous) - (down))) ++ ++static int cw_get_soc(struct cw_battery *cw_bat) ++{ ++ unsigned int soc; ++ int ret; ++ ++ ret = regmap_read(cw_bat->regmap, CW2015_REG_SOC, &soc); ++ if (ret) ++ return ret; ++ ++ if (soc > 100) { ++ int max_error_cycles = ++ CW2015_BAT_SOC_ERROR_MS / cw_bat->poll_interval_ms; ++ ++ dev_err(cw_bat->dev, "Invalid SoC %d%%\n", soc); ++ cw_bat->read_errors++; ++ if (cw_bat->read_errors > max_error_cycles) { ++ dev_warn(cw_bat->dev, ++ "Too many invalid SoC reports, resetting gauge\n"); ++ cw_power_on_reset(cw_bat); ++ cw_bat->read_errors = 0; ++ } ++ return cw_bat->soc; ++ } ++ cw_bat->read_errors = 0; ++ ++ /* Reset gauge if stuck while charging */ ++ if (cw_bat->status == POWER_SUPPLY_STATUS_CHARGING && soc == cw_bat->soc) { ++ int max_stuck_cycles = ++ CW2015_BAT_CHARGING_STUCK_MS / cw_bat->poll_interval_ms; ++ ++ cw_bat->charge_stuck_cnt++; ++ if (cw_bat->charge_stuck_cnt > max_stuck_cycles) { ++ dev_warn(cw_bat->dev, ++ "SoC stuck @%u%%, resetting gauge\n", soc); ++ cw_power_on_reset(cw_bat); ++ cw_bat->charge_stuck_cnt = 0; ++ } ++ } else { ++ cw_bat->charge_stuck_cnt = 0; ++ } ++ ++ /* Ignore voltage dips during charge */ ++ if (cw_bat->charger_attached && HYSTERESIS(soc, cw_bat->soc, 0, 3)) ++ soc = cw_bat->soc; ++ ++ /* Ignore voltage spikes during discharge */ ++ if (!cw_bat->charger_attached && HYSTERESIS(soc, cw_bat->soc, 3, 0)) ++ soc = cw_bat->soc; ++ ++ return soc; ++} ++ ++static int cw_get_voltage(struct cw_battery *cw_bat) ++{ ++ int ret, i, voltage_mv; ++ u16 reg_val; ++ u32 avg = 0; ++ ++ for (i = 0; i < CW2015_AVERAGING_SAMPLES; i++) { ++ ret = cw_read_word(cw_bat, CW2015_REG_VCELL, ®_val); ++ if (ret) ++ return ret; ++ ++ avg += reg_val; ++ } ++ avg /= CW2015_AVERAGING_SAMPLES; ++ ++ /* ++ * 305 uV per ADC step ++ * Use 312 / 1024 as efficient approximation of 305 / 1000 ++ * Negligible error of 0.1% ++ */ ++ voltage_mv = avg * 312 / 1024; ++ ++ dev_dbg(cw_bat->dev, "Read voltage: %d mV, raw=0x%04x\n", ++ voltage_mv, reg_val); ++ return voltage_mv; ++} ++ ++static int cw_get_time_to_empty(struct cw_battery *cw_bat) ++{ ++ int ret; ++ u16 value16; ++ ++ ret = cw_read_word(cw_bat, CW2015_REG_RRT_ALERT, &value16); ++ if (ret) ++ return ret; ++ ++ return value16 & CW2015_MASK_SOC; ++} ++ ++static void cw_update_charge_status(struct cw_battery *cw_bat) ++{ ++ int ret; ++ ++ ret = power_supply_am_i_supplied(cw_bat->rk_bat); ++ if (ret < 0) { ++ dev_warn(cw_bat->dev, "Failed to get supply state: %d\n", ret); ++ } else { ++ bool charger_attached; ++ ++ charger_attached = !!ret; ++ if (cw_bat->charger_attached != charger_attached) { ++ cw_bat->battery_changed = true; ++ if (charger_attached) ++ cw_bat->charge_count++; ++ } ++ cw_bat->charger_attached = charger_attached; ++ } ++} ++ ++static void cw_update_soc(struct cw_battery *cw_bat) ++{ ++ int soc; ++ ++ soc = cw_get_soc(cw_bat); ++ if (soc < 0) ++ dev_err(cw_bat->dev, "Failed to get SoC from gauge: %d\n", soc); ++ else if (cw_bat->soc != soc) { ++ cw_bat->soc = soc; ++ cw_bat->battery_changed = true; ++ } ++} ++ ++static void cw_update_voltage(struct cw_battery *cw_bat) ++{ ++ int voltage_mv; ++ ++ voltage_mv = cw_get_voltage(cw_bat); ++ if (voltage_mv < 0) ++ dev_err(cw_bat->dev, "Failed to get voltage from gauge: %d\n", ++ voltage_mv); ++ else ++ cw_bat->voltage_mv = voltage_mv; ++} ++ ++static void cw_update_status(struct cw_battery *cw_bat) ++{ ++ int status = POWER_SUPPLY_STATUS_DISCHARGING; ++ ++ if (cw_bat->charger_attached) { ++ if (cw_bat->soc >= 100) ++ status = POWER_SUPPLY_STATUS_FULL; ++ else ++ status = POWER_SUPPLY_STATUS_CHARGING; ++ } ++ ++ if (cw_bat->status != status) ++ cw_bat->battery_changed = true; ++ cw_bat->status = status; ++} ++ ++static void cw_update_time_to_empty(struct cw_battery *cw_bat) ++{ ++ int time_to_empty; ++ ++ time_to_empty = cw_get_time_to_empty(cw_bat); ++ if (time_to_empty < 0) ++ dev_err(cw_bat->dev, "Failed to get time to empty from gauge: %d\n", ++ time_to_empty); ++ else if (cw_bat->time_to_empty != time_to_empty) { ++ cw_bat->time_to_empty = time_to_empty; ++ cw_bat->battery_changed = true; ++ } ++} ++ ++static void cw_bat_work(struct work_struct *work) ++{ ++ struct delayed_work *delay_work; ++ struct cw_battery *cw_bat; ++ int ret; ++ unsigned int reg_val; ++ ++ delay_work = to_delayed_work(work); ++ cw_bat = container_of(delay_work, struct cw_battery, battery_delay_work); ++ ret = regmap_read(cw_bat->regmap, CW2015_REG_MODE, ®_val); ++ if (ret) { ++ dev_err(cw_bat->dev, "Failed to read mode from gauge: %d\n", ret); ++ } else { ++ if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) { ++ int i; ++ ++ for (i = 0; i < CW2015_RESET_TRIES; i++) { ++ if (!cw_power_on_reset(cw_bat)) ++ break; ++ } ++ } ++ cw_update_soc(cw_bat); ++ cw_update_voltage(cw_bat); ++ cw_update_charge_status(cw_bat); ++ cw_update_status(cw_bat); ++ cw_update_time_to_empty(cw_bat); ++ } ++ dev_dbg(cw_bat->dev, "charger_attached = %d\n", cw_bat->charger_attached); ++ dev_dbg(cw_bat->dev, "status = %d\n", cw_bat->status); ++ dev_dbg(cw_bat->dev, "soc = %d%%\n", cw_bat->soc); ++ dev_dbg(cw_bat->dev, "voltage = %dmV\n", cw_bat->voltage_mv); ++ ++ if (cw_bat->battery_changed) ++ power_supply_changed(cw_bat->rk_bat); ++ cw_bat->battery_changed = false; ++ ++ queue_delayed_work(cw_bat->battery_workqueue, ++ &cw_bat->battery_delay_work, ++ msecs_to_jiffies(cw_bat->poll_interval_ms)); ++} ++ ++static bool cw_battery_valid_time_to_empty(struct cw_battery *cw_bat) ++{ ++ return cw_bat->time_to_empty > 0 && ++ cw_bat->time_to_empty < CW2015_MASK_SOC && ++ cw_bat->status == POWER_SUPPLY_STATUS_DISCHARGING; ++} ++ ++static int cw_battery_get_property(struct power_supply *psy, ++ enum power_supply_property psp, ++ union power_supply_propval *val) ++{ ++ struct cw_battery *cw_bat; ++ ++ cw_bat = power_supply_get_drvdata(psy); ++ switch (psp) { ++ case POWER_SUPPLY_PROP_CAPACITY: ++ val->intval = cw_bat->soc; ++ break; ++ ++ case POWER_SUPPLY_PROP_STATUS: ++ val->intval = cw_bat->status; ++ break; ++ ++ case POWER_SUPPLY_PROP_PRESENT: ++ val->intval = !!cw_bat->voltage_mv; ++ break; ++ ++ case POWER_SUPPLY_PROP_VOLTAGE_NOW: ++ val->intval = cw_bat->voltage_mv * 1000; ++ break; ++ ++ case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW: ++ if (cw_battery_valid_time_to_empty(cw_bat)) ++ val->intval = cw_bat->time_to_empty; ++ else ++ val->intval = 0; ++ break; ++ ++ case POWER_SUPPLY_PROP_TECHNOLOGY: ++ val->intval = POWER_SUPPLY_TECHNOLOGY_LION; ++ break; ++ ++ case POWER_SUPPLY_PROP_CHARGE_COUNTER: ++ val->intval = cw_bat->charge_count; ++ break; ++ ++ case POWER_SUPPLY_PROP_CHARGE_FULL: ++ case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: ++ if (cw_bat->battery.charge_full_design_uah > 0) ++ val->intval = cw_bat->battery.charge_full_design_uah; ++ else ++ val->intval = 0; ++ break; ++ ++ case POWER_SUPPLY_PROP_CURRENT_NOW: ++ if (cw_battery_valid_time_to_empty(cw_bat) && ++ cw_bat->battery.charge_full_design_uah > 0) { ++ /* calculate remaining capacity */ ++ val->intval = cw_bat->battery.charge_full_design_uah; ++ val->intval = val->intval * cw_bat->soc / 100; ++ ++ /* estimate current based on time to empty */ ++ val->intval = 60 * val->intval / cw_bat->time_to_empty; ++ } else { ++ val->intval = 0; ++ } ++ ++ break; ++ ++ default: ++ break; ++ } ++ return 0; ++} ++ ++static enum power_supply_property cw_battery_properties[] = { ++ POWER_SUPPLY_PROP_CAPACITY, ++ POWER_SUPPLY_PROP_STATUS, ++ POWER_SUPPLY_PROP_PRESENT, ++ POWER_SUPPLY_PROP_VOLTAGE_NOW, ++ POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW, ++ POWER_SUPPLY_PROP_TECHNOLOGY, ++ POWER_SUPPLY_PROP_CHARGE_COUNTER, ++ POWER_SUPPLY_PROP_CHARGE_FULL, ++ POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, ++ POWER_SUPPLY_PROP_CURRENT_NOW, ++}; ++ ++static const struct power_supply_desc cw2015_bat_desc = { ++ .name = "cw2015-battery", ++ .type = POWER_SUPPLY_TYPE_BATTERY, ++ .properties = cw_battery_properties, ++ .num_properties = ARRAY_SIZE(cw_battery_properties), ++ .get_property = cw_battery_get_property, ++}; ++ ++static int cw2015_parse_properties(struct cw_battery *cw_bat) ++{ ++ struct device *dev = cw_bat->dev; ++ int length; ++ int ret; ++ ++ length = device_property_count_u8(dev, "cellwise,battery-profile"); ++ if (length < 0) { ++ dev_warn(cw_bat->dev, ++ "No battery-profile found, using current flash contents\n"); ++ } else if (length != CW2015_SIZE_BATINFO) { ++ dev_err(cw_bat->dev, "battery-profile must be %d bytes\n", ++ CW2015_SIZE_BATINFO); ++ return -EINVAL; ++ } else { ++ cw_bat->bat_profile = devm_kzalloc(dev, length, GFP_KERNEL); ++ if (!cw_bat->bat_profile) ++ return -ENOMEM; ++ ++ ret = device_property_read_u8_array(dev, ++ "cellwise,battery-profile", ++ cw_bat->bat_profile, ++ length); ++ if (ret) ++ return ret; ++ } ++ ++ ret = device_property_read_u32(dev, "cellwise,monitor-interval-ms", ++ &cw_bat->poll_interval_ms); ++ if (ret) { ++ dev_dbg(cw_bat->dev, "Using default poll interval\n"); ++ cw_bat->poll_interval_ms = CW2015_DEFAULT_POLL_INTERVAL_MS; ++ } ++ ++ return 0; ++} ++ ++static const struct regmap_range regmap_ranges_rd_yes[] = { ++ regmap_reg_range(CW2015_REG_VERSION, CW2015_REG_VERSION), ++ regmap_reg_range(CW2015_REG_VCELL, CW2015_REG_CONFIG), ++ regmap_reg_range(CW2015_REG_MODE, CW2015_REG_MODE), ++ regmap_reg_range(CW2015_REG_BATINFO, ++ CW2015_REG_BATINFO + CW2015_SIZE_BATINFO - 1), ++}; ++ ++static const struct regmap_access_table regmap_rd_table = { ++ .yes_ranges = regmap_ranges_rd_yes, ++ .n_yes_ranges = 4, ++}; ++ ++static const struct regmap_range regmap_ranges_wr_yes[] = { ++ regmap_reg_range(CW2015_REG_RRT_ALERT, CW2015_REG_CONFIG), ++ regmap_reg_range(CW2015_REG_MODE, CW2015_REG_MODE), ++ regmap_reg_range(CW2015_REG_BATINFO, ++ CW2015_REG_BATINFO + CW2015_SIZE_BATINFO - 1), ++}; ++ ++static const struct regmap_access_table regmap_wr_table = { ++ .yes_ranges = regmap_ranges_wr_yes, ++ .n_yes_ranges = 3, ++}; ++ ++static const struct regmap_range regmap_ranges_vol_yes[] = { ++ regmap_reg_range(CW2015_REG_VCELL, CW2015_REG_SOC + 1), ++}; ++ ++static const struct regmap_access_table regmap_vol_table = { ++ .yes_ranges = regmap_ranges_vol_yes, ++ .n_yes_ranges = 1, ++}; ++ ++static const struct regmap_config cw2015_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .rd_table = ®map_rd_table, ++ .wr_table = ®map_wr_table, ++ .volatile_table = ®map_vol_table, ++ .max_register = CW2015_REG_BATINFO + CW2015_SIZE_BATINFO - 1, ++}; ++ ++static int cw_bat_probe(struct i2c_client *client) ++{ ++ int ret; ++ struct cw_battery *cw_bat; ++ struct power_supply_config psy_cfg = { 0 }; ++ ++ cw_bat = devm_kzalloc(&client->dev, sizeof(*cw_bat), GFP_KERNEL); ++ if (!cw_bat) ++ return -ENOMEM; ++ ++ i2c_set_clientdata(client, cw_bat); ++ cw_bat->dev = &client->dev; ++ cw_bat->soc = 1; ++ ++ ret = cw2015_parse_properties(cw_bat); ++ if (ret) { ++ dev_err(cw_bat->dev, "Failed to parse cw2015 properties\n"); ++ return ret; ++ } ++ ++ cw_bat->regmap = devm_regmap_init_i2c(client, &cw2015_regmap_config); ++ if (IS_ERR(cw_bat->regmap)) { ++ dev_err(cw_bat->dev, "Failed to allocate regmap: %ld\n", ++ PTR_ERR(cw_bat->regmap)); ++ return PTR_ERR(cw_bat->regmap); ++ } ++ ++ ret = cw_init(cw_bat); ++ if (ret) { ++ dev_err(cw_bat->dev, "Init failed: %d\n", ret); ++ return ret; ++ } ++ ++ psy_cfg.drv_data = cw_bat; ++ psy_cfg.fwnode = dev_fwnode(cw_bat->dev); ++ ++ cw_bat->rk_bat = devm_power_supply_register(&client->dev, ++ &cw2015_bat_desc, ++ &psy_cfg); ++ if (IS_ERR(cw_bat->rk_bat)) { ++ dev_err(cw_bat->dev, "Failed to register power supply\n"); ++ return PTR_ERR(cw_bat->rk_bat); ++ } ++ ++ ret = power_supply_get_battery_info(cw_bat->rk_bat, &cw_bat->battery); ++ if (ret) { ++ dev_warn(cw_bat->dev, ++ "No monitored battery, some properties will be missing\n"); ++ } ++ ++ cw_bat->battery_workqueue = create_singlethread_workqueue("rk_battery"); ++ INIT_DELAYED_WORK(&cw_bat->battery_delay_work, cw_bat_work); ++ queue_delayed_work(cw_bat->battery_workqueue, ++ &cw_bat->battery_delay_work, msecs_to_jiffies(10)); ++ return 0; ++} ++ ++static int __maybe_unused cw_bat_suspend(struct device *dev) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ struct cw_battery *cw_bat = i2c_get_clientdata(client); ++ ++ cancel_delayed_work_sync(&cw_bat->battery_delay_work); ++ return 0; ++} ++ ++static int __maybe_unused cw_bat_resume(struct device *dev) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ struct cw_battery *cw_bat = i2c_get_clientdata(client); ++ ++ queue_delayed_work(cw_bat->battery_workqueue, ++ &cw_bat->battery_delay_work, 0); ++ return 0; ++} ++ ++SIMPLE_DEV_PM_OPS(cw_bat_pm_ops, cw_bat_suspend, cw_bat_resume); ++ ++static int cw_bat_remove(struct i2c_client *client) ++{ ++ struct cw_battery *cw_bat = i2c_get_clientdata(client); ++ ++ cancel_delayed_work_sync(&cw_bat->battery_delay_work); ++ power_supply_put_battery_info(cw_bat->rk_bat, &cw_bat->battery); ++ return 0; ++} ++ ++static const struct i2c_device_id cw_bat_id_table[] = { ++ { "cw2015", 0 }, ++ { } ++}; ++ ++static const struct of_device_id cw2015_of_match[] = { ++ { .compatible = "cellwise,cw2015" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, cw2015_of_match); ++ ++static struct i2c_driver cw_bat_driver = { ++ .driver = { ++ .name = "cw2015", ++ .of_match_table = cw2015_of_match, ++ .pm = &cw_bat_pm_ops, ++ }, ++ .probe_new = cw_bat_probe, ++ .remove = cw_bat_remove, ++ .id_table = cw_bat_id_table, ++}; ++ ++module_i2c_driver(cw_bat_driver); ++ ++MODULE_AUTHOR("xhc"); ++MODULE_AUTHOR("Tobias Schramm "); ++MODULE_DESCRIPTION("cw2015/cw2013 battery driver"); ++MODULE_LICENSE("GPL"); +-- +2.25.4 + + +From 898965fd3ac726e4ac2901ec0abb370e1968f4a5 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:01:59 +0200 +Subject: [PATCH 02/25] leds: Add support for inverted LED triggers + +Needs to be changed for upstream, invert via sysfs not trigger duplication + +Signed-off-by: Tobias Schramm +--- + drivers/leds/led-core.c | 1 + + drivers/leds/led-triggers.c | 148 +++++++++++++++++++++++++++--------- + include/linux/leds.h | 1 + + 3 files changed, 112 insertions(+), 38 deletions(-) + +diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c +index f1f718dbe0f8..f174611e869f 100644 +--- a/drivers/leds/led-core.c ++++ b/drivers/leds/led-core.c +@@ -175,6 +175,7 @@ static void led_blink_setup(struct led_classdev *led_cdev, + unsigned long *delay_off) + { + if (!test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags) && ++ !test_bit(LED_BLINK_INVERT, &led_cdev->work_flags) && + led_cdev->blink_set && + !led_cdev->blink_set(led_cdev, delay_on, delay_off)) + return; +diff --git a/drivers/leds/led-triggers.c b/drivers/leds/led-triggers.c +index 79e30d2cb7a5..c40c58c6e345 100644 +--- a/drivers/leds/led-triggers.c ++++ b/drivers/leds/led-triggers.c +@@ -27,14 +27,80 @@ LIST_HEAD(trigger_list); + + /* Used by LED Class */ + ++#define TRIGGER_INVERT_SUFFIX "-inverted" ++ ++/* ++ * Check suffix of trigger name agains TRIGGER_INVERT_SUFFIX ++ */ ++static bool led_trigger_is_inverted(const char *trigname) ++{ ++ if (strlen(trigname) >= strlen(TRIGGER_INVERT_SUFFIX)) { ++ return !strcmp(trigname + strlen(trigname) - ++ strlen(TRIGGER_INVERT_SUFFIX), ++ TRIGGER_INVERT_SUFFIX); ++ } ++ ++ return false; ++} ++ ++/* ++ * Get length of trigger name name without TRIGGER_INVERT_SUFFIX ++ */ ++static size_t led_trigger_get_name_len(const char *trigname) ++{ ++ // Subtract length of TRIGGER_INVERT_SUFFIX if trigger is inverted ++ if (led_trigger_is_inverted(trigname)) ++ return strlen(trigname) - strlen(TRIGGER_INVERT_SUFFIX); ++ return strlen(trigname); ++} ++ ++/* ++ * Find and set led trigger by name ++ */ ++static int led_trigger_set_str_(struct led_classdev *led_cdev, ++ const char *trigname, bool lock) ++{ ++ struct led_trigger *trig; ++ bool inverted = led_trigger_is_inverted(trigname); ++ size_t len = led_trigger_get_name_len(trigname); ++ ++ down_read(&triggers_list_lock); ++ list_for_each_entry(trig, &trigger_list, next_trig) { ++ /* Compare trigger name without inversion suffix */ ++ if (strlen(trig->name) == len && ++ !strncmp(trigname, trig->name, len)) { ++ if (lock) ++ down_write(&led_cdev->trigger_lock); ++ led_trigger_set(led_cdev, trig); ++ if (inverted) ++ led_cdev->flags |= LED_INVERT_TRIGGER; ++ else ++ led_cdev->flags &= ~LED_INVERT_TRIGGER; ++ if (lock) ++ up_write(&led_cdev->trigger_lock); ++ ++ up_read(&triggers_list_lock); ++ return 0; ++ } ++ } ++ /* we come here only if trigname matches no trigger */ ++ up_read(&triggers_list_lock); ++ return -EINVAL; ++} ++ ++#define led_trigger_set_str(cdev, name) led_trigger_set_str_(cdev, name, true) ++#define led_trigger_set_str_unlocked(cdev, name) \ ++ led_trigger_set_str_(cdev, name, false) ++ ++ + ssize_t led_trigger_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t pos, size_t count) + { + struct device *dev = kobj_to_dev(kobj); + struct led_classdev *led_cdev = dev_get_drvdata(dev); +- struct led_trigger *trig; + int ret = count; ++ char *name; + + mutex_lock(&led_cdev->led_access); + +@@ -48,20 +114,10 @@ ssize_t led_trigger_write(struct file *filp, struct kobject *kobj, + goto unlock; + } + +- down_read(&triggers_list_lock); +- list_for_each_entry(trig, &trigger_list, next_trig) { +- if (sysfs_streq(buf, trig->name)) { +- down_write(&led_cdev->trigger_lock); +- led_trigger_set(led_cdev, trig); +- up_write(&led_cdev->trigger_lock); +- +- up_read(&triggers_list_lock); +- goto unlock; +- } +- } +- /* we come here only if buf matches no trigger */ +- ret = -EINVAL; +- up_read(&triggers_list_lock); ++ name = strim(buf); ++ ret = led_trigger_set_str(led_cdev, name); ++ if (!ret) ++ ret = count; + + unlock: + mutex_unlock(&led_cdev->led_access); +@@ -93,12 +149,22 @@ static int led_trigger_format(char *buf, size_t size, + led_cdev->trigger ? "none" : "[none]"); + + list_for_each_entry(trig, &trigger_list, next_trig) { +- bool hit = led_cdev->trigger && +- !strcmp(led_cdev->trigger->name, trig->name); ++ bool hit = led_cdev->trigger == trig; ++ bool inverted = led_cdev->flags & LED_INVERT_TRIGGER; ++ ++ /* print non-inverted trigger */ ++ len += led_trigger_snprintf(buf + len, size - len, ++ " %s%s%s", ++ hit && !inverted ? "[" : "", ++ trig->name, ++ hit && !inverted ? "]" : ""); + ++ /* print inverted trigger */ + len += led_trigger_snprintf(buf + len, size - len, +- " %s%s%s", hit ? "[" : "", +- trig->name, hit ? "]" : ""); ++ " %s%s"TRIGGER_INVERT_SUFFIX"%s", ++ hit && inverted ? "[" : "", ++ trig->name, ++ hit && inverted ? "]" : ""); + } + + len += led_trigger_snprintf(buf + len, size - len, "\n"); +@@ -235,21 +301,15 @@ EXPORT_SYMBOL_GPL(led_trigger_remove); + + void led_trigger_set_default(struct led_classdev *led_cdev) + { +- struct led_trigger *trig; ++ bool found; + + if (!led_cdev->default_trigger) + return; + + down_read(&triggers_list_lock); +- down_write(&led_cdev->trigger_lock); +- list_for_each_entry(trig, &trigger_list, next_trig) { +- if (!strcmp(led_cdev->default_trigger, trig->name)) { +- led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER; +- led_trigger_set(led_cdev, trig); +- break; +- } +- } +- up_write(&led_cdev->trigger_lock); ++ found = !led_trigger_set_str(led_cdev, led_cdev->default_trigger); ++ if (found) ++ led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER; + up_read(&triggers_list_lock); + } + EXPORT_SYMBOL_GPL(led_trigger_set_default); +@@ -292,11 +352,14 @@ int led_trigger_register(struct led_trigger *trig) + /* Register with any LEDs that have this as a default trigger */ + down_read(&leds_list_lock); + list_for_each_entry(led_cdev, &leds_list, node) { ++ bool found; ++ + down_write(&led_cdev->trigger_lock); +- if (!led_cdev->trigger && led_cdev->default_trigger && +- !strcmp(led_cdev->default_trigger, trig->name)) { +- led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER; +- led_trigger_set(led_cdev, trig); ++ if (!led_cdev->trigger && led_cdev->default_trigger) { ++ found = !led_trigger_set_str_unlocked(led_cdev, ++ led_cdev->default_trigger); ++ if (found) ++ led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER; + } + up_write(&led_cdev->trigger_lock); + } +@@ -369,8 +432,14 @@ void led_trigger_event(struct led_trigger *trig, + return; + + read_lock(&trig->leddev_list_lock); +- list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list) +- led_set_brightness(led_cdev, brightness); ++ list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list) { ++ /* Reverse brightness if LED is inverted */ ++ if (led_cdev->flags & LED_INVERT_TRIGGER) ++ led_set_brightness(led_cdev, ++ led_cdev->max_brightness - brightness); ++ else ++ led_set_brightness(led_cdev, brightness); ++ } + read_unlock(&trig->leddev_list_lock); + } + EXPORT_SYMBOL_GPL(led_trigger_event); +@@ -388,10 +457,13 @@ static void led_trigger_blink_setup(struct led_trigger *trig, + + read_lock(&trig->leddev_list_lock); + list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list) { +- if (oneshot) ++ bool trigger_inverted = ++ !!(led_cdev->flags & LED_INVERT_TRIGGER); ++ if (oneshot) { ++ /* use logical xnor to determine inversion parameter */ + led_blink_set_oneshot(led_cdev, delay_on, delay_off, +- invert); +- else ++ (!!invert) == trigger_inverted); ++ } else + led_blink_set(led_cdev, delay_on, delay_off); + } + read_unlock(&trig->leddev_list_lock); +diff --git a/include/linux/leds.h b/include/linux/leds.h +index 2451962d1ec5..c15298502b39 100644 +--- a/include/linux/leds.h ++++ b/include/linux/leds.h +@@ -75,6 +75,7 @@ struct led_classdev { + #define LED_BRIGHT_HW_CHANGED BIT(21) + #define LED_RETAIN_AT_SHUTDOWN BIT(22) + #define LED_INIT_DEFAULT_TRIGGER BIT(23) ++#define LED_INVERT_TRIGGER BIT(24) + + /* set_brightness_work / blink_timer flags, atomic, private. */ + unsigned long work_flags; +-- +2.25.4 + + +From c6366d834561973fdbff6a26e359ae6604bad782 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:06:20 +0200 +Subject: [PATCH 03/25] soc: rockchip: Add rockchip suspend mode driver + +Code gore, do not mainline. This belongs in ATF + +Signed-off-by: Tobias Schramm +--- + .../soc/rockchip/rockchip-pm-config.txt | 39 ++++ + drivers/soc/rockchip/Kconfig | 6 + + drivers/soc/rockchip/Makefile | 1 + + drivers/soc/rockchip/rockchip_pm_config.c | 212 ++++++++++++++++++ + include/dt-bindings/suspend/rockchip-rk3399.h | 60 +++++ + 5 files changed, 318 insertions(+) + create mode 100644 Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt + create mode 100644 drivers/soc/rockchip/rockchip_pm_config.c + create mode 100644 include/dt-bindings/suspend/rockchip-rk3399.h + +diff --git a/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt b/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt +new file mode 100644 +index 000000000000..a8fd70f17597 +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt +@@ -0,0 +1,39 @@ ++* the suspend mode config ++ ++- compatible: "rockchip,pm-config" ++ Compatibility with rk3399 ++ ++- rockchip,sleep-mode-config : the sleep mode config, ++ ARMOFF, OSC disabled ... ++ ++- rockchip,wakeup-config: the wake up sourece enable. ++ GPIO, USB, SD... ++ ++- rockchip,pwm-regulator-config: the pwm regulator name. ++ ++Example: ++ rockchip_suspend: rockchip_suspend { ++ compatible = "rockchip,pm-rk3399"; ++ status = "okay"; ++ rockchip,sleep-mode-config = < ++ (0 ++ | RKPM_SLP_ARMPD ++ | RKPM_SLP_PERILPPD ++ | RKPM_SLP_DDR_RET ++ | RKPM_SLP_PLLPD ++ | RKPM_SLP_OSC_DIS ++ | RKPM_SLP_CENTER_PD ++ | RKPM_SLP_AP_PWROFF ++ ) ++ >; ++ rockchip,wakeup-config = < ++ (0 | ++ RKPM_GPIO_WKUP_EN | ++ RKPM_PWM_WKUP_EN) ++ >; ++ rockchip,pwm-regulator-config = < ++ (0 | ++ PWM2_REGULATOR_EN ++ ) ++ >; ++ }; +diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig +index b71b73bf5fc5..bfadbecd0df8 100644 +--- a/drivers/soc/rockchip/Kconfig ++++ b/drivers/soc/rockchip/Kconfig +@@ -26,4 +26,10 @@ config ROCKCHIP_PM_DOMAINS + + If unsure, say N. + ++config ROCKCHIP_SUSPEND_MODE ++ bool "Rockchip suspend mode config" ++ depends on ROCKCHIP_SIP ++ help ++ Say Y here if you want to set the suspend mode to the ATF. ++ + endif +diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile +index afca0a4c4b72..a15c0a395a33 100644 +--- a/drivers/soc/rockchip/Makefile ++++ b/drivers/soc/rockchip/Makefile +@@ -4,3 +4,4 @@ + # + obj-$(CONFIG_ROCKCHIP_GRF) += grf.o + obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o ++obj-$(CONFIG_ROCKCHIP_SUSPEND_MODE) += rockchip_pm_config.o +diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c +new file mode 100644 +index 000000000000..43b2e0f33343 +--- /dev/null ++++ b/drivers/soc/rockchip/rockchip_pm_config.c +@@ -0,0 +1,212 @@ ++/* ++ * Rockchip Generic power configuration support. ++ * ++ * Copyright (c) 2017 ROCKCHIP, Co. Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PM_INVALID_GPIO 0xffff ++ ++static const struct of_device_id pm_match_table[] = { ++ { .compatible = "rockchip,pm-rk3399",}, ++ { }, ++}; ++ ++#define MAX_PWRKEY_NUMS 20 ++#define MAX_NUM_KEYS 60 ++ ++struct rkxx_remote_key_table { ++ int scancode; ++ int keycode; ++}; ++ ++static int parse_ir_pwrkeys(unsigned int *pwrkey, int size, int *nkey) ++{ ++ struct device_node *node; ++ struct device_node *child_node; ++ struct rkxx_remote_key_table key_table[MAX_NUM_KEYS]; ++ int i; ++ int len = 0, nbuttons; ++ int num = 0; ++ u32 usercode, scancode; ++ ++ for_each_node_by_name(node, "pwm") { ++ for_each_child_of_node(node, child_node) { ++ if (of_property_read_u32(child_node, ++ "rockchip,usercode", ++ &usercode)) ++ break; ++ ++ if (of_get_property(child_node, ++ "rockchip,key_table", ++ &len) == NULL || ++ len <= 0) ++ break; ++ ++ len = len < sizeof(key_table) ? len : sizeof(key_table); ++ len /= sizeof(u32); ++ if (of_property_read_u32_array(child_node, ++ "rockchip,key_table", ++ (u32 *)key_table, ++ len)) ++ break; ++ ++ nbuttons = len / 2; ++ for (i = 0; i < nbuttons && num < size; ++i) { ++ if (key_table[i].keycode == KEY_POWER) { ++ scancode = key_table[i].scancode; ++ pr_debug("usercode=%x, key=%x\n", ++ usercode, scancode); ++ pwrkey[num] = (usercode & 0xffff) << 16; ++ pwrkey[num] |= (scancode & 0xff) << 8; ++ ++num; ++ } ++ } ++ } ++ } ++ ++ *nkey = num; ++ ++ return num ? 0 : -1; ++} ++ ++static void rockchip_pm_virt_pwroff_prepare(void) ++{ ++ int error; ++ int i, nkey; ++ u32 power_key[MAX_PWRKEY_NUMS]; ++ ++ if ((parse_ir_pwrkeys(power_key, ARRAY_SIZE(power_key), &nkey))) { ++ pr_err("Parse ir powerkey code failed!\n"); ++ return; ++ } ++ ++ for (i = 0; i < nkey; ++i) ++ sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 1, power_key[i]); ++ ++ regulator_suspend_prepare(PM_SUSPEND_MEM); ++ ++ error = disable_nonboot_cpus(); ++ if (error) { ++ pr_err("Disable nonboot cpus failed!\n"); ++ return; ++ } ++ ++ sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 1); ++ sip_smc_virtual_poweroff(); ++} ++ ++static int __init pm_config_init(struct platform_device *pdev) ++{ ++ const struct of_device_id *match_id; ++ struct device_node *node; ++ u32 mode_config = 0; ++ u32 wakeup_config = 0; ++ u32 pwm_regulator_config = 0; ++ int gpio_temp[10]; ++ u32 sleep_debug_en = 0; ++ u32 apios_suspend = 0; ++ u32 virtual_poweroff_en = 0; ++ enum of_gpio_flags flags; ++ int i = 0; ++ int length; ++ ++ match_id = of_match_node(pm_match_table, pdev->dev.of_node); ++ if (!match_id) ++ return -ENODEV; ++ ++ node = of_find_node_by_name(NULL, "rockchip-suspend"); ++ ++ if (IS_ERR_OR_NULL(node)) { ++ dev_err(&pdev->dev, "%s dev node err\n", __func__); ++ return -ENODEV; ++ } ++ ++ if (of_property_read_u32_array(node, ++ "rockchip,sleep-mode-config", ++ &mode_config, 1)) ++ dev_warn(&pdev->dev, "not set sleep mode config\n"); ++ else ++ sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, mode_config, 0); ++ ++ if (of_property_read_u32_array(node, ++ "rockchip,wakeup-config", ++ &wakeup_config, 1)) ++ dev_warn(&pdev->dev, "not set wakeup-config\n"); ++ else ++ sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, wakeup_config, 0); ++ ++ if (of_property_read_u32_array(node, ++ "rockchip,pwm-regulator-config", ++ &pwm_regulator_config, 1)) ++ dev_warn(&pdev->dev, "not set pwm-regulator-config\n"); ++ else ++ sip_smc_set_suspend_mode(PWM_REGULATOR_CONFIG, ++ pwm_regulator_config, ++ 0); ++ ++ length = of_gpio_named_count(node, "rockchip,power-ctrl"); ++ ++ if (length > 0 && length < 10) { ++ for (i = 0; i < length; i++) { ++ gpio_temp[i] = of_get_named_gpio_flags(node, ++ "rockchip,power-ctrl", ++ i, ++ &flags); ++ if (!gpio_is_valid(gpio_temp[i])) ++ break; ++ sip_smc_set_suspend_mode(GPIO_POWER_CONFIG, ++ i, ++ gpio_temp[i]); ++ } ++ } ++ sip_smc_set_suspend_mode(GPIO_POWER_CONFIG, i, PM_INVALID_GPIO); ++ ++ if (!of_property_read_u32_array(node, ++ "rockchip,sleep-debug-en", ++ &sleep_debug_en, 1)) ++ sip_smc_set_suspend_mode(SUSPEND_DEBUG_ENABLE, ++ sleep_debug_en, ++ 0); ++ ++ if (!of_property_read_u32_array(node, ++ "rockchip,apios-suspend", ++ &apios_suspend, 1)) ++ sip_smc_set_suspend_mode(APIOS_SUSPEND_CONFIG, ++ apios_suspend, ++ 0); ++ ++ if (!of_property_read_u32_array(node, ++ "rockchip,virtual-poweroff", ++ &virtual_poweroff_en, 1) && ++ virtual_poweroff_en) ++ pm_power_off_prepare = rockchip_pm_virt_pwroff_prepare; ++ ++ return 0; ++} ++ ++static struct platform_driver pm_driver = { ++ .driver = { ++ .name = "rockchip-pm", ++ .of_match_table = pm_match_table, ++ }, ++}; ++ ++static int __init rockchip_pm_drv_register(void) ++{ ++ return platform_driver_probe(&pm_driver, pm_config_init); ++} ++subsys_initcall(rockchip_pm_drv_register); +diff --git a/include/dt-bindings/suspend/rockchip-rk3399.h b/include/dt-bindings/suspend/rockchip-rk3399.h +new file mode 100644 +index 000000000000..0cccd6430ef6 +--- /dev/null ++++ b/include/dt-bindings/suspend/rockchip-rk3399.h +@@ -0,0 +1,60 @@ ++/* ++ * Header providing constants for Rockchip suspend bindings. ++ * ++ * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd ++ * Author: Tony.Xie ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__ ++#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__ ++ ++/* the suspend mode */ ++#define RKPM_SLP_WFI (1 << 0) ++#define RKPM_SLP_ARMPD (1 << 1) ++#define RKPM_SLP_PERILPPD (1 << 2) ++#define RKPM_SLP_DDR_RET (1 << 3) ++#define RKPM_SLP_PLLPD (1 << 4) ++#define RKPM_SLP_OSC_DIS (1 << 5) ++#define RKPM_SLP_CENTER_PD (1 << 6) ++#define RKPM_SLP_AP_PWROFF (1 << 7) ++ ++/* the wake up source */ ++#define RKPM_CLUSTER_L_WKUP_EN (1 << 0) ++#define RKPM_CLUSTER_B_WKUPB_EN (1 << 1) ++#define RKPM_GPIO_WKUP_EN (1 << 2) ++#define RKPM_SDIO_WKUP_EN (1 << 3) ++#define RKPM_SDMMC_WKUP_EN (1 << 4) ++#define RKPM_TIMER_WKUP_EN (1 << 6) ++#define RKPM_USB_WKUP_EN (1 << 7) ++#define RKPM_SFT_WKUP_EN (1 << 8) ++#define RKPM_WDT_M0_WKUP_EN (1 << 9) ++#define RKPM_TIME_OUT_WKUP_EN (1 << 10) ++#define RKPM_PWM_WKUP_EN (1 << 11) ++#define RKPM_PCIE_WKUP_EN (1 << 13) ++ ++/* the pwm regulator */ ++#define PWM0_REGULATOR_EN (1 << 0) ++#define PWM1_REGULATOR_EN (1 << 1) ++#define PWM2_REGULATOR_EN (1 << 2) ++#define PWM3A_REGULATOR_EN (1 << 3) ++#define PWM3B_REGULATOR_EN (1 << 4) ++ ++/* the APIO voltage domain */ ++#define RKPM_APIO0_SUSPEND (1 << 0) ++#define RKPM_APIO1_SUSPEND (1 << 1) ++#define RKPM_APIO2_SUSPEND (1 << 2) ++#define RKPM_APIO3_SUSPEND (1 << 3) ++#define RKPM_APIO4_SUSPEND (1 << 4) ++#define RKPM_APIO5_SUSPEND (1 << 5) ++ ++#endif +-- +2.25.4 + + +From 0f4359f32783d6b1ca731e30eba8f2af64b23114 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:11:05 +0200 +Subject: [PATCH 04/25] firmware: Add Rockchip SIP driver + +Used exclusively for suspend signaling. Drop for mainline and +use PSCI + +Signed-off-by: Tobias Schramm +--- + drivers/firmware/Kconfig | 7 + + drivers/firmware/Makefile | 1 + + drivers/firmware/rockchip_sip.c | 262 ++++++++++++++++++++++++++ + include/linux/rockchip/rockchip_sip.h | 149 +++++++++++++++ + 4 files changed, 419 insertions(+) + create mode 100644 drivers/firmware/rockchip_sip.c + create mode 100644 include/linux/rockchip/rockchip_sip.h + +diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig +index 8007d4aa76dc..37f8039a5e27 100644 +--- a/drivers/firmware/Kconfig ++++ b/drivers/firmware/Kconfig +@@ -298,6 +298,13 @@ config TURRIS_MOX_RWTM + config HAVE_ARM_SMCCC + bool + ++config ROCKCHIP_SIP ++ bool "Rockchip SIP interface" ++ depends on ARM64 && ARM_PSCI_FW ++ help ++ Say Y here if you want to enable SIP callbacks for Rockchip platforms ++ This option enables support for communicating with the ATF. ++ + source "drivers/firmware/psci/Kconfig" + source "drivers/firmware/broadcom/Kconfig" + source "drivers/firmware/google/Kconfig" +diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile +index e9fb838af4df..575f45d55939 100644 +--- a/drivers/firmware/Makefile ++++ b/drivers/firmware/Makefile +@@ -29,6 +29,7 @@ obj-y += meson/ + obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ + obj-$(CONFIG_EFI) += efi/ + obj-$(CONFIG_UEFI_CPER) += efi/ ++obj-$(CONFIG_ROCKCHIP_SIP) += rockchip_sip.o + obj-y += imx/ + obj-y += tegra/ + obj-y += xilinx/ +diff --git a/drivers/firmware/rockchip_sip.c b/drivers/firmware/rockchip_sip.c +new file mode 100644 +index 000000000000..6ed780c587e1 +--- /dev/null ++++ b/drivers/firmware/rockchip_sip.c +@@ -0,0 +1,262 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_64BIT ++#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name ++#else ++#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name ++#endif ++ ++#define SIZE_PAGE(n) ((n) << 12) ++ ++static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id, ++ unsigned long arg0, ++ unsigned long arg1, ++ unsigned long arg2) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); ++ return res; ++} ++ ++struct arm_smccc_res sip_smc_ddr_cfg(u32 arg0, u32 arg1, u32 arg2) ++{ ++ return __invoke_sip_fn_smc(SIP_DDR_CFG, arg0, arg1, arg2); ++} ++ ++struct arm_smccc_res sip_smc_get_atf_version(void) ++{ ++ return __invoke_sip_fn_smc(SIP_ATF_VERSION, 0, 0, 0); ++} ++ ++struct arm_smccc_res sip_smc_get_sip_version(void) ++{ ++ return __invoke_sip_fn_smc(SIP_SIP_VERSION, 0, 0, 0); ++} ++ ++int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2) ++{ ++ struct arm_smccc_res res; ++ ++ res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, ctrl, config1, config2); ++ return res.a0; ++} ++ ++int sip_smc_virtual_poweroff(void) ++{ ++ struct arm_smccc_res res; ++ ++ res = __invoke_sip_fn_smc(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), 0, 0, 0); ++ return res.a0; ++} ++ ++struct arm_smccc_res sip_smc_request_share_mem(u32 page_num, ++ share_page_type_t page_type) ++{ ++ struct arm_smccc_res res; ++ unsigned long share_mem_phy; ++ ++ res = __invoke_sip_fn_smc(SIP_SHARE_MEM, page_num, page_type, 0); ++ if (IS_SIP_ERROR(res.a0)) ++ goto error; ++ ++ share_mem_phy = res.a1; ++ res.a1 = (unsigned long)ioremap(share_mem_phy, SIZE_PAGE(page_num)); ++ ++error: ++ return res; ++} ++ ++struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2) ++{ ++ return __invoke_sip_fn_smc(SIP_MCU_EL3FIQ_CFG, arg0, arg1, arg2); ++} ++ ++/************************** fiq debugger **************************************/ ++#ifdef CONFIG_ARM64 ++#define SIP_UARTDBG_FN SIP_UARTDBG_CFG64 ++#else ++#define SIP_UARTDBG_FN SIP_UARTDBG_CFG ++#endif ++ ++static int fiq_sip_enabled; ++static int fiq_target_cpu; ++static phys_addr_t ft_fiq_mem_phy; ++static void __iomem *ft_fiq_mem_base; ++static void (*sip_fiq_debugger_uart_irq_tf)(struct pt_regs _pt_regs, ++ unsigned long cpu); ++int sip_fiq_debugger_is_enabled(void) ++{ ++ return fiq_sip_enabled; ++} ++ ++static struct pt_regs sip_fiq_debugger_get_pt_regs(void *reg_base, ++ unsigned long sp_el1) ++{ ++ struct pt_regs fiq_pt_regs; ++ ++#ifdef CONFIG_ARM64 ++ /* copy cpu context */ ++ memcpy(&fiq_pt_regs, reg_base, 8 * 31); ++ ++ /* copy pstate */ ++ memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8); ++ ++ /* EL1 mode */ ++ if (fiq_pt_regs.pstate & 0x10) ++ memcpy(&fiq_pt_regs.sp, reg_base + 0xf8, 8); ++ /* EL0 mode */ ++ else ++ fiq_pt_regs.sp = sp_el1; ++ ++ /* copy pc */ ++ memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8); ++#else ++ struct sm_nsec_ctx *nsec_ctx = reg_base; ++ ++ fiq_pt_regs.ARM_r0 = nsec_ctx->r0; ++ fiq_pt_regs.ARM_r1 = nsec_ctx->r1; ++ fiq_pt_regs.ARM_r2 = nsec_ctx->r2; ++ fiq_pt_regs.ARM_r3 = nsec_ctx->r3; ++ fiq_pt_regs.ARM_r4 = nsec_ctx->r4; ++ fiq_pt_regs.ARM_r5 = nsec_ctx->r5; ++ fiq_pt_regs.ARM_r6 = nsec_ctx->r6; ++ fiq_pt_regs.ARM_r7 = nsec_ctx->r7; ++ fiq_pt_regs.ARM_r8 = nsec_ctx->r8; ++ fiq_pt_regs.ARM_r9 = nsec_ctx->r9; ++ fiq_pt_regs.ARM_r10 = nsec_ctx->r10; ++ fiq_pt_regs.ARM_fp = nsec_ctx->r11; ++ fiq_pt_regs.ARM_ip = nsec_ctx->r12; ++ fiq_pt_regs.ARM_sp = nsec_ctx->svc_sp; ++ fiq_pt_regs.ARM_lr = nsec_ctx->svc_lr; ++ fiq_pt_regs.ARM_pc = nsec_ctx->mon_lr; ++ fiq_pt_regs.ARM_cpsr = nsec_ctx->mon_spsr; ++#endif ++ ++ return fiq_pt_regs; ++} ++ ++static void sip_fiq_debugger_uart_irq_tf_cb(unsigned long sp_el1, ++ unsigned long offset, ++ unsigned long cpu) ++{ ++ struct pt_regs fiq_pt_regs; ++ char *cpu_context; ++ ++ /* calling fiq handler */ ++ if (ft_fiq_mem_base) { ++ cpu_context = (char *)ft_fiq_mem_base + offset; ++ fiq_pt_regs = sip_fiq_debugger_get_pt_regs(cpu_context, sp_el1); ++ sip_fiq_debugger_uart_irq_tf(fiq_pt_regs, cpu); ++ } ++ ++ /* fiq handler done, return to EL3(then EL3 return to EL1 entry) */ ++ __invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, UARTDBG_CFG_OSHDL_TO_OS); ++} ++ ++int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn) ++{ ++ struct arm_smccc_res res; ++ ++ fiq_target_cpu = 0; ++ ++ /* init fiq debugger callback */ ++ sip_fiq_debugger_uart_irq_tf = callback_fn; ++ res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, irq_id, ++ (unsigned long)sip_fiq_debugger_uart_irq_tf_cb, ++ UARTDBG_CFG_INIT); ++ if (IS_SIP_ERROR(res.a0)) { ++ pr_err("%s error: %d\n", __func__, (int)res.a0); ++ return res.a0; ++ } ++ ++ /* share memory ioremap */ ++ if (!ft_fiq_mem_base) { ++ ft_fiq_mem_phy = res.a1; ++ ft_fiq_mem_base = ioremap(ft_fiq_mem_phy, ++ FIQ_UARTDBG_SHARE_MEM_SIZE); ++ if (!ft_fiq_mem_base) { ++ pr_err("%s: share memory ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ } ++ ++ fiq_sip_enabled = 1; ++ ++ return SIP_RET_SUCCESS; ++} ++ ++int sip_fiq_debugger_switch_cpu(u32 cpu) ++{ ++ struct arm_smccc_res res; ++ ++ fiq_target_cpu = cpu; ++ res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, cpu_logical_map(cpu), ++ 0, UARTDBG_CFG_OSHDL_CPUSW); ++ return res.a0; ++} ++ ++void sip_fiq_debugger_enable_debug(bool enable) ++{ ++ unsigned long val; ++ ++ val = enable ? UARTDBG_CFG_OSHDL_DEBUG_ENABLE : ++ UARTDBG_CFG_OSHDL_DEBUG_DISABLE; ++ ++ __invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, val); ++} ++ ++int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate) ++{ ++ struct arm_smccc_res res; ++ ++ res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, port_phyaddr, baudrate, ++ UARTDBG_CFG_PRINT_PORT); ++ return res.a0; ++} ++ ++int sip_fiq_debugger_request_share_memory(void) ++{ ++ struct arm_smccc_res res; ++ ++ /* request page share memory */ ++ res = sip_smc_request_share_mem(FIQ_UARTDBG_PAGE_NUMS, ++ SHARE_PAGE_TYPE_UARTDBG); ++ if (IS_SIP_ERROR(res.a0)) ++ return res.a0; ++ ++ return SIP_RET_SUCCESS; ++} ++ ++int sip_fiq_debugger_get_target_cpu(void) ++{ ++ return fiq_target_cpu; ++} ++ ++void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu) ++{ ++ u32 en; ++ ++ fiq_target_cpu = tgt_cpu; ++ en = enable ? UARTDBG_CFG_FIQ_ENABEL : UARTDBG_CFG_FIQ_DISABEL; ++ __invoke_sip_fn_smc(SIP_UARTDBG_FN, tgt_cpu, 0, en); ++} +diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h +new file mode 100644 +index 000000000000..b19f64ede981 +--- /dev/null ++++ b/include/linux/rockchip/rockchip_sip.h +@@ -0,0 +1,149 @@ ++/* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#ifndef __ROCKCHIP_SIP_H ++#define __ROCKCHIP_SIP_H ++ ++#include ++#include ++ ++/* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */ ++#define SIP_ATF_VERSION 0x82000001 ++#define SIP_ACCESS_REG 0x82000002 ++#define SIP_SUSPEND_MODE 0x82000003 ++#define SIP_PENDING_CPUS 0x82000004 ++#define SIP_UARTDBG_CFG 0x82000005 ++#define SIP_UARTDBG_CFG64 0xc2000005 ++#define SIP_MCU_EL3FIQ_CFG 0x82000006 ++#define SIP_ACCESS_CHIP_STATE64 0xc2000006 ++#define SIP_SECURE_MEM_CONFIG 0x82000007 ++#define SIP_ACCESS_CHIP_EXTRA_STATE64 0xc2000007 ++#define SIP_DDR_CFG 0x82000008 ++#define SIP_SHARE_MEM 0x82000009 ++#define SIP_SIP_VERSION 0x8200000a ++#define SIP_REMOTECTL_CFG 0x8200000b ++ ++/* Trust firmware version */ ++#define ATF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff) ++#define ATF_VER_MINOR(ver) (((ver) >> 0) & 0xffff) ++ ++/* SIP_ACCESS_REG: read or write */ ++#define SECURE_REG_RD 0x0 ++#define SECURE_REG_WR 0x1 ++ ++/* Fiq debugger share memory: 8KB enough */ ++#define FIQ_UARTDBG_PAGE_NUMS 2 ++#define FIQ_UARTDBG_SHARE_MEM_SIZE ((FIQ_UARTDBG_PAGE_NUMS) * 4096) ++ ++/* Error return code */ ++#define IS_SIP_ERROR(x) (!!(x)) ++ ++#define SIP_RET_SUCCESS 0 ++#define SIP_RET_SMC_UNKNOWN -1 ++#define SIP_RET_NOT_SUPPORTED -2 ++#define SIP_RET_INVALID_PARAMS -3 ++#define SIP_RET_INVALID_ADDRESS -4 ++#define SIP_RET_DENIED -5 ++ ++/* SIP_UARTDBG_CFG64 call types */ ++#define UARTDBG_CFG_INIT 0xf0 ++#define UARTDBG_CFG_OSHDL_TO_OS 0xf1 ++#define UARTDBG_CFG_OSHDL_CPUSW 0xf3 ++#define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4 ++#define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5 ++#define UARTDBG_CFG_PRINT_PORT 0xf7 ++#define UARTDBG_CFG_FIQ_ENABEL 0xf8 ++#define UARTDBG_CFG_FIQ_DISABEL 0xf9 ++ ++/* SIP_SUSPEND_MODE32 call types */ ++#define SUSPEND_MODE_CONFIG 0x01 ++#define WKUP_SOURCE_CONFIG 0x02 ++#define PWM_REGULATOR_CONFIG 0x03 ++#define GPIO_POWER_CONFIG 0x04 ++#define SUSPEND_DEBUG_ENABLE 0x05 ++#define APIOS_SUSPEND_CONFIG 0x06 ++#define VIRTUAL_POWEROFF 0x07 ++ ++/* SIP_REMOTECTL_CFG call types */ ++#define REMOTECTL_SET_IRQ 0xf0 ++#define REMOTECTL_SET_PWM_CH 0xf1 ++#define REMOTECTL_SET_PWRKEY 0xf2 ++#define REMOTECTL_GET_WAKEUP_STATE 0xf3 ++#define REMOTECTL_ENABLE 0xf4 ++/* wakeup state */ ++#define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf ++ ++/* Share mem page types */ ++typedef enum { ++ SHARE_PAGE_TYPE_INVALID = 0, ++ SHARE_PAGE_TYPE_UARTDBG, ++ SHARE_PAGE_TYPE_MAX, ++} share_page_type_t; ++ ++/* ++ * Rules: struct arm_smccc_res contains result and data, details: ++ * ++ * a0: error code(0: success, !0: error); ++ * a1~a3: data ++ */ ++struct arm_smccc_res sip_smc_get_atf_version(void); ++struct arm_smccc_res sip_smc_get_sip_version(void); ++struct arm_smccc_res sip_smc_ddr_cfg(u32 arg0, u32 arg1, u32 arg2); ++struct arm_smccc_res sip_smc_request_share_mem(u32 page_num, ++ share_page_type_t page_type); ++struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2); ++ ++int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2); ++int sip_smc_virtual_poweroff(void); ++/***************************fiq debugger **************************************/ ++void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu); ++void sip_fiq_debugger_enable_debug(bool enable); ++int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn); ++int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate); ++int sip_fiq_debugger_request_share_memory(void); ++int sip_fiq_debugger_get_target_cpu(void); ++int sip_fiq_debugger_switch_cpu(u32 cpu); ++int sip_fiq_debugger_is_enabled(void); ++ ++/* optee cpu_context */ ++struct sm_nsec_ctx { ++ u32 usr_sp; ++ u32 usr_lr; ++ u32 irq_spsr; ++ u32 irq_sp; ++ u32 irq_lr; ++ u32 svc_spsr; ++ u32 svc_sp; ++ u32 svc_lr; ++ u32 abt_spsr; ++ u32 abt_sp; ++ u32 abt_lr; ++ u32 und_spsr; ++ u32 und_sp; ++ u32 und_lr; ++ u32 mon_lr; ++ u32 mon_spsr; ++ u32 r4; ++ u32 r5; ++ u32 r6; ++ u32 r7; ++ u32 r8; ++ u32 r9; ++ u32 r10; ++ u32 r11; ++ u32 r12; ++ u32 r0; ++ u32 r1; ++ u32 r2; ++ u32 r3; ++}; ++ ++#endif +-- +2.25.4 + + +From 56a1d88ef4af3e9b34f90cac46dec3ec3546efeb Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:12:56 +0200 +Subject: [PATCH 05/25] tty: serdev: support shutdown op + +Allow serdev drivers to register a shutdown handler + +Signed-off-by: Tobias Schramm +--- + drivers/tty/serdev/core.c | 11 +++++++++++ + include/linux/serdev.h | 1 + + 2 files changed, 12 insertions(+) + +diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c +index c5f0d936b003..37e45c356540 100644 +--- a/drivers/tty/serdev/core.c ++++ b/drivers/tty/serdev/core.c +@@ -432,11 +432,22 @@ static int serdev_drv_remove(struct device *dev) + return 0; + } + ++static void serdev_drv_shutdown(struct device *dev) ++{ ++ const struct serdev_device_driver *sdrv; ++ if (dev->driver) { ++ sdrv = to_serdev_device_driver(dev->driver); ++ if (sdrv->shutdown) ++ sdrv->shutdown(to_serdev_device(dev)); ++ } ++} ++ + static struct bus_type serdev_bus_type = { + .name = "serial", + .match = serdev_device_match, + .probe = serdev_drv_probe, + .remove = serdev_drv_remove, ++ .shutdown = serdev_drv_shutdown, + }; + + /** +diff --git a/include/linux/serdev.h b/include/linux/serdev.h +index 9f14f9c12ec4..94050561325c 100644 +--- a/include/linux/serdev.h ++++ b/include/linux/serdev.h +@@ -63,6 +63,7 @@ struct serdev_device_driver { + struct device_driver driver; + int (*probe)(struct serdev_device *); + void (*remove)(struct serdev_device *); ++ void (*shutdown)(struct serdev_device *); + }; + + static inline struct serdev_device_driver *to_serdev_device_driver(struct device_driver *d) +-- +2.25.4 + + +From 6f9e10d6bcb68ec3db1bc45ac6eeff22d73e84e2 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:14:06 +0200 +Subject: [PATCH 06/25] bluetooth: hci_serdev: Clear registered bit on + unregister + +Signed-off-by: Tobias Schramm +--- + drivers/bluetooth/hci_serdev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c +index 4652896d4990..72270f01e580 100644 +--- a/drivers/bluetooth/hci_serdev.c ++++ b/drivers/bluetooth/hci_serdev.c +@@ -364,5 +364,7 @@ void hci_uart_unregister_device(struct hci_uart *hu) + + hu->proto->close(hu); + serdev_device_close(hu->serdev); ++ ++ clear_bit(HCI_UART_REGISTERED, &hu->flags); + } + EXPORT_SYMBOL_GPL(hci_uart_unregister_device); +-- +2.25.4 + + +From 5c1ccc765769979b0c440840801a9a821c89087e Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:15:08 +0200 +Subject: [PATCH 07/25] bluetooth: hci_bcm: disable power on shutdown + +Firmware behaves wonky when not power cycled over reboots + +Signed-off-by: Tobias Schramm +--- + drivers/bluetooth/hci_bcm.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c +index b236cb11c0dc..4c0b79393ced 100644 +--- a/drivers/bluetooth/hci_bcm.c ++++ b/drivers/bluetooth/hci_bcm.c +@@ -1472,6 +1472,23 @@ static void bcm_serdev_remove(struct serdev_device *serdev) + hci_uart_unregister_device(&bcmdev->serdev_hu); + } + ++static void bcm_serdev_shutdown(struct serdev_device *serdev) ++{ ++ struct bcm_device *bcmdev = serdev_device_get_drvdata(serdev); ++ ++/* ++ if (test_bit(HCI_UART_REGISTERED, &bcmdev->hu->flags)) { ++ hci_uart_unregister_device(&bcmdev->serdev_hu); ++ } ++*/ ++ dev_info(bcmdev->dev, "Cutting power to bluetooth module\n"); ++ if (bcm_gpio_set_power(bcmdev, false)) { ++ dev_err(bcmdev->dev, "Failed to power down\n"); ++ } ++ usleep_range(500000, 1000000); ++} ++ ++ + #ifdef CONFIG_OF + static struct bcm_device_data bcm4354_device_data = { + .no_early_set_baudrate = true, +@@ -1497,6 +1514,7 @@ MODULE_DEVICE_TABLE(of, bcm_bluetooth_of_match); + static struct serdev_device_driver bcm_serdev_driver = { + .probe = bcm_serdev_probe, + .remove = bcm_serdev_remove, ++ .shutdown = bcm_serdev_shutdown, + .driver = { + .name = "hci_uart_bcm", + .of_match_table = of_match_ptr(bcm_bluetooth_of_match), +-- +2.25.4 + + +From 4cac229795f388f45f2c32cbdc47ce9088be2129 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:16:52 +0200 +Subject: [PATCH 08/25] mmc: core: pwrseq_simple: disable mmc power on shutdown + +Fix for Broadcom SDIO WiFi modules. They misbehave if reinitialized +without a power cycle. + +Signed-off-by: Tobias Schramm +--- + drivers/mmc/core/pwrseq_simple.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c +index ea4d3670560e..38fe7e29aba6 100644 +--- a/drivers/mmc/core/pwrseq_simple.c ++++ b/drivers/mmc/core/pwrseq_simple.c +@@ -80,10 +80,8 @@ static void mmc_pwrseq_simple_post_power_on(struct mmc_host *host) + msleep(pwrseq->post_power_on_delay_ms); + } + +-static void mmc_pwrseq_simple_power_off(struct mmc_host *host) ++static void __mmc_pwrseq_simple_power_off(struct mmc_pwrseq_simple *pwrseq) + { +- struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); +- + mmc_pwrseq_simple_set_gpios_value(pwrseq, 1); + + if (pwrseq->power_off_delay_us) +@@ -96,6 +94,12 @@ static void mmc_pwrseq_simple_power_off(struct mmc_host *host) + } + } + ++static void mmc_pwrseq_simple_power_off(struct mmc_host *host) ++{ ++ struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); ++ __mmc_pwrseq_simple_power_off(pwrseq); ++} ++ + static const struct mmc_pwrseq_ops mmc_pwrseq_simple_ops = { + .pre_power_on = mmc_pwrseq_simple_pre_power_on, + .post_power_on = mmc_pwrseq_simple_post_power_on, +@@ -151,9 +155,18 @@ static int mmc_pwrseq_simple_remove(struct platform_device *pdev) + return 0; + } + ++static void mmc_pwrseq_simple_shutdown(struct platform_device *pdev) ++{ ++ struct mmc_pwrseq_simple *pwrseq = platform_get_drvdata(pdev); ++ ++ dev_info(&pdev->dev, "Turning off mmc\n"); ++ __mmc_pwrseq_simple_power_off(pwrseq); ++} ++ + static struct platform_driver mmc_pwrseq_simple_driver = { + .probe = mmc_pwrseq_simple_probe, + .remove = mmc_pwrseq_simple_remove, ++ .shutdown = mmc_pwrseq_simple_shutdown, + .driver = { + .name = "pwrseq_simple", + .of_match_table = mmc_pwrseq_simple_of_match, +-- +2.25.4 + + +From 170d9b07db07142f8200c3454f43369c4ff893b4 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:19:31 +0200 +Subject: [PATCH 09/25] regulator: core: add generic suspend states support + +This commit adds genric suspend support for regualtors without +explicit suspend ops. +Not sure if this would be accepted mainline, the reinitialization +procedure might be unsafe. + +Signed-off-by: Tobias Schramm +--- + drivers/regulator/core.c | 48 +++++++++++++++++++++++++++++--- + include/linux/regulator/driver.h | 3 ++ + 2 files changed, 47 insertions(+), 4 deletions(-) + +diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c +index 7486f6e4e613..b03b00ea5a53 100644 +--- a/drivers/regulator/core.c ++++ b/drivers/regulator/core.c +@@ -5268,6 +5268,14 @@ void regulator_unregister(struct regulator_dev *rdev) + EXPORT_SYMBOL_GPL(regulator_unregister); + + #ifdef CONFIG_SUSPEND ++static inline int can_enable(struct regulator_dev *rdev) { ++ return rdev->ena_pin || rdev->desc->ops->enable; ++} ++ ++static inline int can_disable(struct regulator_dev *rdev) { ++ return rdev->ena_pin || rdev->desc->ops->disable; ++} ++ + /** + * regulator_suspend - prepare regulators for system wide suspend + * @dev: ``&struct device`` pointer that is passed to _regulator_suspend() +@@ -5278,10 +5286,33 @@ static int regulator_suspend(struct device *dev) + { + struct regulator_dev *rdev = dev_to_rdev(dev); + suspend_state_t state = pm_suspend_target_state; ++ struct regulator_state *rstate; + int ret; + + regulator_lock(rdev); + ret = suspend_set_state(rdev, state); ++ if (ret) { ++ goto out; ++ } ++ ++ rstate = regulator_get_suspend_state(rdev, state); ++ if (rstate == NULL) ++ goto out; ++ ++ if (rstate->enabled == ENABLE_IN_SUSPEND && can_enable(rdev)) { ++ if (!rdev->desc->ops->set_suspend_enable) { ++ rdev->resume_state = _regulator_is_enabled(rdev); ++ rdev_info(rdev, "Entering suspend %d, enabling forcibly, was %s\n", state, rdev->resume_state ? "on" : "off"); ++ ret = _regulator_do_enable(rdev); ++ } ++ } else if (rstate->enabled == DISABLE_IN_SUSPEND && can_disable(rdev)) { ++ if (!rdev->desc->ops->set_suspend_disable) { ++ rdev->resume_state = _regulator_is_enabled(rdev); ++ rdev_info(rdev, "Entering suspend %d, disabling forcibly, was %s\n", state, rdev->resume_state ? "on" : "off"); ++ ret = _regulator_do_disable(rdev); ++ } ++ } ++out: + regulator_unlock(rdev); + + return ret; +@@ -5300,10 +5331,19 @@ static int regulator_resume(struct device *dev) + + regulator_lock(rdev); + +- if (rdev->desc->ops->resume && +- (rstate->enabled == ENABLE_IN_SUSPEND || +- rstate->enabled == DISABLE_IN_SUSPEND)) +- ret = rdev->desc->ops->resume(rdev); ++ if (rstate->enabled == ENABLE_IN_SUSPEND || rstate->enabled == DISABLE_IN_SUSPEND) { ++ if (rdev->desc->ops->resume) { ++ ret = rdev->desc->ops->resume(rdev); ++ } else if ((rstate->enabled == ENABLE_IN_SUSPEND && !rdev->desc->ops->set_suspend_enable) || ++ (rstate->enabled == DISABLE_IN_SUSPEND && !rdev->desc->ops->set_suspend_disable)) { ++ rdev_info(rdev, "Resuming, restoring state to %s\n", rdev->resume_state ? "on" : "off"); ++ if (rdev->resume_state && can_enable(rdev)) { ++ ret = _regulator_do_enable(rdev); ++ } else if (!rdev->resume_state && can_disable(rdev)) { ++ ret = _regulator_do_disable(rdev); ++ } ++ } ++ } + + regulator_unlock(rdev); + +diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h +index 29d920516e0b..549b68c58e68 100644 +--- a/include/linux/regulator/driver.h ++++ b/include/linux/regulator/driver.h +@@ -482,6 +482,9 @@ struct regulator_dev { + + /* time when this regulator was disabled last time */ + unsigned long last_off_jiffy; ++ ++ /* state when resuming */ ++ int resume_state; + }; + + struct regulator_dev * +-- +2.25.4 + + +From b8ea100dcfc176fce064748f6a68e815ef37e87c Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:22:09 +0200 +Subject: [PATCH 10/25] usb: typec: bus: Catch crash due to partner NULL value + +Think this has been fixed upstream, have not seen it happen for ages. +Drop on next rebase. + +Signed-off-by: Tobias Schramm +--- + drivers/usb/typec/bus.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/typec/bus.c b/drivers/usb/typec/bus.c +index e8ddb81cb6df..1d0265f46441 100644 +--- a/drivers/usb/typec/bus.c ++++ b/drivers/usb/typec/bus.c +@@ -154,8 +154,14 @@ EXPORT_SYMBOL_GPL(typec_altmode_exit); + */ + void typec_altmode_attention(struct typec_altmode *adev, u32 vdo) + { +- struct typec_altmode *pdev = &to_altmode(adev)->partner->adev; ++ struct typec_altmode *pdev; ++ WARN_ONCE(!adev, "typec bus attention: adev is NULL!"); ++ WARN_ONCE(!to_altmode(adev)->partner, "typec bus attention: partner is NULL!"); ++ if(!adev || !to_altmode(adev)->partner) { ++ return; ++ } + ++ pdev = &to_altmode(adev)->partner->adev; + if (pdev->ops && pdev->ops->attention) + pdev->ops->attention(pdev, vdo); + } +-- +2.25.4 + + +From 6a0d6deeac14f5347dd1310fdcbe8f510b29cfee Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:23:54 +0200 +Subject: [PATCH 11/25] usb: typec: tcpm: add hacky generic altmode support + +This is a hack and it is based on extcon. Do not try to mainline +unless you are in need for some retroactive abortion by the +maintainers. + +Signed-off-by: Tobias Schramm +--- + drivers/usb/typec/tcpm/tcpm.c | 140 +++++++++++++++++++++++++++++++++- + 1 file changed, 139 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c +index 82b19ebd7838..9858df11590b 100644 +--- a/drivers/usb/typec/tcpm/tcpm.c ++++ b/drivers/usb/typec/tcpm/tcpm.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -322,6 +323,12 @@ struct tcpm_port { + /* port belongs to a self powered device */ + bool self_powered; + ++ ++#ifdef CONFIG_EXTCON ++ struct extcon_dev *extcon; ++ unsigned int *extcon_cables; ++#endif ++ + #ifdef CONFIG_DEBUG_FS + struct dentry *dentry; + struct mutex logbuffer_lock; /* log buffer access lock */ +@@ -607,6 +614,35 @@ static void tcpm_debugfs_exit(const struct tcpm_port *port) { } + + #endif + ++static void tcpm_update_extcon_data(struct tcpm_port *port, bool attached) { ++#ifdef CONFIG_EXTCON ++ unsigned int *capability = port->extcon_cables; ++ if (port->data_role == TYPEC_HOST) { ++ extcon_set_state(port->extcon, EXTCON_USB, false); ++ extcon_set_state(port->extcon, EXTCON_USB_HOST, attached); ++ } else { ++ extcon_set_state(port->extcon, EXTCON_USB, true); ++ extcon_set_state(port->extcon, EXTCON_USB_HOST, attached); ++ } ++ while (*capability != EXTCON_NONE) { ++ if (attached) { ++ union extcon_property_value val; ++ val.intval = (port->polarity == TYPEC_POLARITY_CC2); ++ extcon_set_property(port->extcon, *capability, ++ EXTCON_PROP_USB_TYPEC_POLARITY, val); ++ } else { ++ extcon_set_state(port->extcon, *capability, false); ++ } ++ extcon_sync(port->extcon, *capability); ++ capability++; ++ } ++ tcpm_log(port, "Extcon update (%s): %s, %s", ++ attached ? "attached" : "detached", ++ port->data_role == TYPEC_HOST ? "host" : "device", ++ port->polarity == TYPEC_POLARITY_CC1 ? "normal" : "flipped"); ++#endif ++} ++ + static int tcpm_pd_transmit(struct tcpm_port *port, + enum tcpm_transmit_type type, + const struct pd_message *msg) +@@ -834,6 +870,8 @@ static int tcpm_set_roles(struct tcpm_port *port, bool attached, + typec_set_data_role(port->typec_port, data); + typec_set_pwr_role(port->typec_port, role); + ++ tcpm_update_extcon_data(port, attached); ++ + return 0; + } + +@@ -1044,7 +1082,7 @@ static void svdm_consume_modes(struct tcpm_port *port, const __le32 *payload, + paltmode->mode = i; + paltmode->vdo = le32_to_cpu(payload[i]); + +- tcpm_log(port, " Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x", ++ tcpm_log(port, "Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x", + pmdata->altmodes, paltmode->svid, + paltmode->mode, paltmode->vdo); + +@@ -1064,6 +1102,9 @@ static void tcpm_register_partner_altmodes(struct tcpm_port *port) + if (!altmode) + tcpm_log(port, "Failed to register partner SVID 0x%04x", + modep->altmode_desc[i].svid); ++ else ++ tcpm_log(port, "Registered altmode 0x%04x", modep->altmode_desc[i].svid); ++ + port->partner_altmode[i] = altmode; + } + } +@@ -1167,9 +1208,11 @@ static int tcpm_pd_svdm(struct tcpm_port *port, const __le32 *payload, int cnt, + modep->svid_index++; + if (modep->svid_index < modep->nsvids) { + u16 svid = modep->svids[modep->svid_index]; ++ tcpm_log(port, "More modes available, sending discover"); + response[0] = VDO(svid, 1, CMD_DISCOVER_MODES); + rlen = 1; + } else { ++ tcpm_log(port, "Got all patner modes, registering"); + tcpm_register_partner_altmodes(port); + } + break; +@@ -2693,6 +2736,7 @@ static int tcpm_src_attach(struct tcpm_port *port) + static void tcpm_typec_disconnect(struct tcpm_port *port) + { + if (port->connected) { ++ tcpm_update_extcon_data(port, false); + typec_unregister_partner(port->partner); + port->partner = NULL; + port->connected = false; +@@ -2750,6 +2794,8 @@ static void tcpm_detach(struct tcpm_port *port) + port->hard_reset_count = 0; + + tcpm_reset_port(port); ++ ++ tcpm_update_extcon_data(port, false); + } + + static void tcpm_src_detach(struct tcpm_port *port) +@@ -4424,6 +4470,64 @@ void tcpm_tcpc_reset(struct tcpm_port *port) + } + EXPORT_SYMBOL_GPL(tcpm_tcpc_reset); + ++unsigned int default_supported_cables[] = { ++ EXTCON_NONE ++}; ++ ++static int tcpm_fw_get_caps_late(struct tcpm_port *port, ++ struct fwnode_handle *fwnode) ++{ ++ int ret, i; ++ ret = fwnode_property_count_u32(fwnode, "typec-altmodes"); ++ if (ret > 0) { ++ u32 *props; ++ if (ret % 4) { ++ dev_err(port->dev, "Length of typec altmode array must be divisible by 4"); ++ return -EINVAL; ++ } ++ ++ props = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL); ++ if (!props) { ++ dev_err(port->dev, "Failed to allocate memory for altmode properties"); ++ return -ENOMEM; ++ } ++ ++ if(fwnode_property_read_u32_array(fwnode, "typec-altmodes", props, ret) < 0) { ++ dev_err(port->dev, "Failed to read altmodes from port"); ++ return -EINVAL; ++ } ++ ++ i = 0; ++ while (ret > 0 && i < ARRAY_SIZE(port->port_altmode)) { ++ struct typec_altmode *alt; ++ struct typec_altmode_desc alt_desc = { ++ .svid = props[i * 4], ++ .mode = props[i * 4 + 1], ++ .vdo = props[i * 4 + 2], ++ .roles = props[i * 4 + 3], ++ }; ++ ++ ++ tcpm_log(port, "Adding altmode SVID: 0x%04x, mode: %d, vdo: %u, role: %d", ++ alt_desc.svid, alt_desc.mode, alt_desc.vdo, alt_desc.roles); ++ alt = typec_port_register_altmode(port->typec_port, ++ &alt_desc); ++ if (IS_ERR(alt)) { ++ tcpm_log(port, ++ "%s: failed to register port alternate mode 0x%x", ++ dev_name(port->dev), alt_desc.svid); ++ break; ++ } ++ typec_altmode_set_drvdata(alt, port); ++ alt->ops = &tcpm_altmode_ops; ++ port->port_altmode[i] = alt; ++ i++; ++ ret -= 4; ++ } ++ } ++ return 0; ++} ++ + static int tcpm_fw_get_caps(struct tcpm_port *port, + struct fwnode_handle *fwnode) + { +@@ -4434,6 +4538,23 @@ static int tcpm_fw_get_caps(struct tcpm_port *port, + if (!fwnode) + return -EINVAL; + ++#ifdef CONFIG_EXTCON ++ ret = fwnode_property_count_u32(fwnode, "extcon-cables"); ++ if (ret > 0) { ++ port->extcon_cables = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL); ++ if (!port->extcon_cables) { ++ dev_err(port->dev, "Failed to allocate memory for extcon cable types. "\ ++ "Using default tyes"); ++ goto extcon_default; ++ } ++ fwnode_property_read_u32_array(fwnode, "extcon-cables", port->extcon_cables, ret); ++ } else { ++extcon_default: ++ dev_info(port->dev, "No cable types defined, using default cables"); ++ port->extcon_cables = default_supported_cables; ++ } ++#endif ++ + /* USB data support is optional */ + ret = fwnode_property_read_string(fwnode, "data-role", &cap_str); + if (ret == 0) { +@@ -4766,6 +4887,17 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) + goto out_destroy_wq; + + port->try_role = port->typec_caps.prefer_role; ++#ifdef CONFIG_EXTCON ++ port->extcon = devm_extcon_dev_allocate(dev, port->extcon_cables); ++ if (IS_ERR(port->extcon)) { ++ dev_err(dev, "Failed to allocate extcon device: %ld", PTR_ERR(port->extcon)); ++ goto out_destroy_wq; ++ } ++ if((err = devm_extcon_dev_register(dev, port->extcon))) { ++ dev_err(dev, "Failed to register extcon device: %d", err); ++ goto out_destroy_wq; ++ } ++#endif + + port->typec_caps.fwnode = tcpc->fwnode; + port->typec_caps.revision = 0x0120; /* Type-C spec release 1.2 */ +@@ -4793,6 +4925,12 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) + goto out_role_sw_put; + } + ++ err = tcpm_fw_get_caps_late(port, tcpc->fwnode); ++ if (err < 0) { ++ dev_err(dev, "Failed to get altmodes from fwnode"); ++ goto out_destroy_wq; ++ } ++ + mutex_lock(&port->lock); + tcpm_init(port); + mutex_unlock(&port->lock); +-- +2.25.4 + + +From d5565800b947e23bc47efa6c26f36e69d54cfd4e Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:25:32 +0200 +Subject: [PATCH 12/25] phy: rockchip: typec: Set extcon capabilities + +Do not mainline, hack. + +Signed-off-by: Tobias Schramm +--- + drivers/phy/rockchip/phy-rockchip-typec.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c +index 24563160197f..f5b497b4b97e 100644 +--- a/drivers/phy/rockchip/phy-rockchip-typec.c ++++ b/drivers/phy/rockchip/phy-rockchip-typec.c +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1160,6 +1161,22 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) + dev_err(dev, "Invalid or missing extcon\n"); + return PTR_ERR(tcphy->extcon); + } ++ } else { ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_sync(tcphy->extcon, EXTCON_USB); ++ extcon_sync(tcphy->extcon, EXTCON_USB_HOST); ++ extcon_sync(tcphy->extcon, EXTCON_DISP_DP); + } + + pm_runtime_enable(dev); +-- +2.25.4 + + +From 82ce1a4cadd37691e59074d03e547a1ea96d9a13 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:26:27 +0200 +Subject: [PATCH 13/25] usb: typec: altmodes: displayport: Add hacky, generic + altmode detection + +Do not mainline, hack. + +Signed-off-by: Tobias Schramm +--- + drivers/usb/typec/altmodes/displayport.c | 55 ++++++++++++++++++++++-- + 1 file changed, 52 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c +index 0edfb89e04a8..c87cd57302cd 100644 +--- a/drivers/usb/typec/altmodes/displayport.c ++++ b/drivers/usb/typec/altmodes/displayport.c +@@ -9,6 +9,8 @@ + */ + + #include ++#include ++#include + #include + #include + #include +@@ -134,15 +136,53 @@ static int dp_altmode_status_update(struct dp_altmode *dp) + return ret; + } + ++static void dp_altmode_update_extcon(struct dp_altmode *dp, bool disconnect) { ++ const struct device *dev = &dp->port->dev; ++ struct extcon_dev* edev = NULL; ++ ++ while (dev) { ++ edev = extcon_find_edev_by_node(dev->of_node); ++ if(!IS_ERR(edev)) { ++ break; ++ } ++ dev = dev->parent; ++ } ++ ++ if (IS_ERR_OR_NULL(edev)) { ++ return; ++ } ++ ++ if (disconnect || !dp->data.conf) { ++ extcon_set_state_sync(edev, EXTCON_DISP_DP, false); ++ } else { ++ union extcon_property_value extcon_true = { .intval = true }; ++ extcon_set_state(edev, EXTCON_DISP_DP, true); ++ if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf) & DP_PIN_ASSIGN_MULTI_FUNC_MASK) { ++ extcon_set_state_sync(edev, EXTCON_USB_HOST, true); ++ extcon_set_property(edev, EXTCON_DISP_DP, EXTCON_PROP_USB_SS, ++ extcon_true); ++ } else { ++ extcon_set_state_sync(edev, EXTCON_USB_HOST, false); ++ } ++ extcon_sync(edev, EXTCON_DISP_DP); ++ extcon_set_state_sync(edev, EXTCON_USB, false); ++ } ++ ++} ++ + static int dp_altmode_configured(struct dp_altmode *dp) + { + int ret; + + sysfs_notify(&dp->alt->dev.kobj, "displayport", "configuration"); + +- if (!dp->data.conf) ++ if (!dp->data.conf) { ++ dp_altmode_update_extcon(dp, true); + return typec_altmode_notify(dp->alt, TYPEC_STATE_USB, + &dp->data); ++ } ++ ++ dp_altmode_update_extcon(dp, false); + + ret = dp_altmode_notify(dp); + if (ret) +@@ -169,9 +209,11 @@ static int dp_altmode_configure_vdm(struct dp_altmode *dp, u32 conf) + if (ret) { + if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf)) + dp_altmode_notify(dp); +- else ++ else { ++ dp_altmode_update_extcon(dp, true); + typec_altmode_notify(dp->alt, TYPEC_STATE_USB, + &dp->data); ++ } + } + + return ret; +@@ -210,6 +252,8 @@ static void dp_altmode_work(struct work_struct *work) + case DP_STATE_EXIT: + if (typec_altmode_exit(dp->alt)) + dev_err(&dp->alt->dev, "Exit Mode Failed!\n"); ++ else ++ dp_altmode_update_extcon(dp, true); + break; + default: + break; +@@ -520,8 +564,13 @@ int dp_altmode_probe(struct typec_altmode *alt) + if (!(DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) & + DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo)) && + !(DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) & +- DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo))) ++ DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo))) { ++ dev_err(&alt->dev, "No compatible pin configuration found:"\ ++ "%04lx -> %04lx, %04lx <- %04lx", ++ DP_CAP_DFP_D_PIN_ASSIGN(port->vdo), DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo), ++ DP_CAP_UFP_D_PIN_ASSIGN(port->vdo), DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo)); + return -ENODEV; ++ } + + ret = sysfs_create_group(&alt->dev.kobj, &dp_altmode_group); + if (ret) +-- +2.25.4 + + +From 5d8a749069f3b822eba0b08733f46f736452e63b Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:34:47 +0200 +Subject: [PATCH 14/25] sound: soc: codecs: es8316: Run micdetect only if jack + status asserted + +Think this is (was?) required to prevent flapping of detection status on +the PBP. + +Signed-off-by: Tobias Schramm +--- + sound/soc/codecs/es8316.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c +index 36eef1fb3d18..b303ebbd5f53 100644 +--- a/sound/soc/codecs/es8316.c ++++ b/sound/soc/codecs/es8316.c +@@ -687,7 +687,7 @@ static void es8316_disable_jack_detect(struct snd_soc_component *component) + snd_soc_component_update_bits(component, ES8316_GPIO_DEBOUNCE, + ES8316_GPIO_ENABLE_INTERRUPT, 0); + +- if (es8316->jack->status & SND_JACK_MICROPHONE) { ++ if (es8316->jack && (es8316->jack->status & SND_JACK_MICROPHONE)) { + es8316_disable_micbias_for_mic_gnd_short_detect(component); + snd_soc_jack_report(es8316->jack, 0, SND_JACK_BTN_0); + } +-- +2.25.4 + + +From 6bd713f297441deb195b51420200cfe1a2739bbe Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:36:47 +0200 +Subject: [PATCH 15/25] ASoC: soc-jack.c: supported inverted jack detect GPIOs + +Signed-off-by: Tobias Schramm +--- + sound/soc/soc-jack.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/soc-jack.c b/sound/soc/soc-jack.c +index b5748dcd490f..a8c199e361e2 100644 +--- a/sound/soc/soc-jack.c ++++ b/sound/soc/soc-jack.c +@@ -254,8 +254,6 @@ static void snd_soc_jack_gpio_detect(struct snd_soc_jack_gpio *gpio) + int report; + + enable = gpiod_get_value_cansleep(gpio->desc); +- if (gpio->invert) +- enable = !enable; + + if (enable) + report = gpio->report; +@@ -384,6 +382,9 @@ int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count, + goto undo; + } + } else { ++ int flags = GPIOF_IN; ++ if (gpios[i].invert) ++ flags |= GPIOF_ACTIVE_LOW; + /* legacy GPIO number */ + if (!gpio_is_valid(gpios[i].gpio)) { + dev_err(jack->card->dev, +@@ -393,7 +394,7 @@ int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count, + goto undo; + } + +- ret = gpio_request_one(gpios[i].gpio, GPIOF_IN, ++ ret = gpio_request_one(gpios[i].gpio, flags, + gpios[i].name); + if (ret) + goto undo; +-- +2.25.4 + + +From d7e2f4a72fed0092a87be90c800db8911f66b5bb Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:38:03 +0200 +Subject: [PATCH 16/25] arm64: dts: rockchip: add default rk3399 + rockchip-suspend node + +Again this has no place in mainline. Should be handled by ATF +and signalled via PSCI. + +Signed-off-by: Tobias Schramm +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 1448f358ed0a..a91fc5c8b43b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + + / { +@@ -2652,4 +2653,27 @@ pcie_clkreqnb_cpm: pci-clkreqnb-cpm { + }; + + }; ++ ++ rockchip_suspend: rockchip-suspend { ++ compatible = "rockchip,pm-rk3399"; ++ status = "disabled"; ++ rockchip,sleep-debug-en = <0>; ++ rockchip,virtual-poweroff = <0>; ++ rockchip,sleep-mode-config = < ++ (0 ++ | RKPM_SLP_ARMPD ++ | RKPM_SLP_PERILPPD ++ | RKPM_SLP_DDR_RET ++ | RKPM_SLP_PLLPD ++ | RKPM_SLP_OSC_DIS ++ | RKPM_SLP_CENTER_PD ++ | RKPM_SLP_AP_PWROFF ++ ) ++ >; ++ rockchip,wakeup-config = < ++ (0 ++ | RKPM_GPIO_WKUP_EN ++ ) ++ >; ++ }; + }; +-- +2.25.4 + + +From 843b3482181b6ad5dcb9861c145c090ee77f7e55 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:39:55 +0200 +Subject: [PATCH 17/25] arm64: dts: rockchip: enable earlycon + +Signed-off-by: Tobias Schramm +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index c49982dfd8fc..b12b19391daa 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -19,6 +19,7 @@ / { + compatible = "pine64,pinebook-pro", "rockchip,rk3399"; + + chosen { ++ bootargs = "earlycon=uart8250,mmio32,0xff1a0000"; + stdout-path = "serial2:1500000n8"; + }; + +-- +2.25.4 + + +From 05723ca70c204c501c48284601bd587807dc0fd5 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:40:31 +0200 +Subject: [PATCH 18/25] arm64: dts: rockchip: reserve memory for ATF rockchip + SIP + +Definitely not for mainline + +Signed-off-by: Tobias Schramm +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index b12b19391daa..85e4b8f9be2a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -23,6 +23,11 @@ chosen { + stdout-path = "serial2:1500000n8"; + }; + ++ memory { ++ device_type = "memory"; ++ reg = <0x0 0x00200000 0x0 0xf7e00000>; ++ }; ++ + backlight: edp-backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_12v>; +@@ -126,6 +131,12 @@ sdio_pwrseq: sdio-pwrseq { + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + ++ /* first 128k(0xff8d0000~0xff8f0000) for ddr and ATF */ ++ sram@ff8d0000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */ ++ }; ++ + /* Audio components */ + es8316-sound { + compatible = "simple-audio-card"; +-- +2.25.4 + + +From e6375ceb68fa97431615e8cc5f379ac806192bae Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:41:41 +0200 +Subject: [PATCH 19/25] arm64: dts: rockchip: add cw2015 fuel gauge + +Signed-off-by: Tobias Schramm +--- + .../boot/dts/rockchip/rk3399-pinebook-pro.dts | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 85e4b8f9be2a..75eebcf4b5e3 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -34,6 +34,13 @@ backlight: edp-backlight { + pwms = <&pwm0 0 740740 0>; + }; + ++ bat: battery { ++ compatible = "simple-battery"; ++ charge-full-design-microamp-hours = <9800000>; ++ voltage-max-design-microvolt = <4350000>; ++ voltage-min-design-microvolt = <3000000>; ++ }; ++ + edp_panel: edp-panel { + compatible = "boe,nv140fhmn49"; + backlight = <&backlight>; +@@ -753,6 +760,24 @@ usbc_dp: endpoint { + }; + }; + }; ++ ++ cw2015@62 { ++ compatible = "cellwise,cw2015"; ++ reg = <0x62>; ++ cellwise,battery-profile = /bits/ 8 < ++ 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 ++ 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 ++ 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 ++ 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 ++ 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 ++ 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D ++ 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB ++ 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 ++ >; ++ cellwise,monitor-interval-ms = <5000>; ++ monitored-battery = <&bat>; ++ power-supplies = <&mains_charger>, <&fusb0>; ++ }; + }; + + &i2s1 { +-- +2.25.4 + + +From 72b64c73b36a2d25e260cb1b4ecb0b8524629c04 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:42:54 +0200 +Subject: [PATCH 20/25] arm64: dts: rockchip: use power led for disk-activity + indication + +Signed-off-by: Tobias Schramm +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 75eebcf4b5e3..56e767a03f85 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -110,7 +110,8 @@ green-led { + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; +- label = "green:power"; ++ label = "green:disk-activity"; ++ linux,default-trigger = "mmc2-inverted"; + }; + + red-led { +-- +2.25.4 + + +From 2aaad78d2b415a27874911937393e68338041b28 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:43:27 +0200 +Subject: [PATCH 21/25] arm64: dts: rockchip: add oficially unsupported 2GHz + opp + +No mainlining here. + +Signed-off-by: Tobias Schramm +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 56e767a03f85..3afd92ed3dde 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -392,6 +392,13 @@ mains_charger: dc-charger { + }; + }; + ++&cluster1_opp { ++ opp08 { ++ opp-hz = /bits/ 64 <2000000000>; ++ opp-microvolt = <1300000>; ++ }; ++}; ++ + &cdn_dp { + status = "okay"; + }; +-- +2.25.4 + + +From 57c61f56278278e71086d28fad8ef700ef8a08e0 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:44:15 +0200 +Subject: [PATCH 22/25] arm64: dts: rockchip: add typec extcon hack + +Not for mainline + +Signed-off-by: Tobias Schramm +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 3afd92ed3dde..27a7b6b5bf52 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -401,6 +401,7 @@ opp08 { + + &cdn_dp { + status = "okay"; ++ extcon = <&fusb0>; + }; + + &cpu_b0 { +@@ -735,6 +736,9 @@ connector { + ; + try-power-role = "sink"; + ++ extcon-cables = <1 2 5 6 9 10 12 44>; ++ typec-altmodes = <0xff01 1 0x001c0000 1>; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; +@@ -1003,6 +1007,7 @@ spiflash: flash@0 { + }; + + &tcphy0 { ++ extcon = <&fusb0>; + status = "okay"; + }; + +-- +2.25.4 + + +From 35f8f124a902c1493a1e70561703f4e5933c18ca Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 14:44:40 +0200 +Subject: [PATCH 23/25] arm64: dts: rockchip: add rockchip-suspend node + +No mainline + +Signed-off-by: Tobias Schramm +--- + .../boot/dts/rockchip/rk3399-pinebook-pro.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 27a7b6b5bf52..e2f83b556b6f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -955,6 +955,29 @@ &pwm2 { + status = "okay"; + }; + ++&rockchip_suspend { ++ status = "okay"; ++ rockchip,sleep-debug-en = <1>; ++ rockchip,sleep-mode-config = < ++ (0 ++ | RKPM_SLP_ARMPD ++ | RKPM_SLP_PERILPPD ++ | RKPM_SLP_DDR_RET ++ | RKPM_SLP_PLLPD ++ | RKPM_SLP_CENTER_PD ++ | RKPM_SLP_AP_PWROFF ++ ) ++ >; ++ rockchip,pwm-regulator-config = < ++ (0 ++ | PWM2_REGULATOR_EN ++ ) ++ >; ++ rockchip,power-ctrl = ++ <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>, ++ <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; ++}; ++ + &saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +-- +2.25.4 + + +From db9a63c28982ab39ffaa5a9fc174bf8d2937619a Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Thu, 28 May 2020 15:20:15 +0200 +Subject: [PATCH 24/25] arm64: configs: add defconfig for Pinebook Pro + +Signed-off-by: Tobias Schramm +--- + arch/arm64/configs/pinebook_pro_defconfig | 3000 +++++++++++++++++++++ + 1 file changed, 3000 insertions(+) + create mode 100644 arch/arm64/configs/pinebook_pro_defconfig + +diff --git a/arch/arm64/configs/pinebook_pro_defconfig b/arch/arm64/configs/pinebook_pro_defconfig +new file mode 100644 +index 000000000000..bc7bcee200e4 +--- /dev/null ++++ b/arch/arm64/configs/pinebook_pro_defconfig +@@ -0,0 +1,3000 @@ ++CONFIG_LOCALVERSION="-MANJARO-ARM" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_GENERIC_IRQ_DEBUGFS=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_PREEMPT_VOLUNTARY=y ++CONFIG_IRQ_TIME_ACCOUNTING=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=23 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=14 ++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=15 ++CONFIG_MEMCG=y ++CONFIG_MEMCG_SWAP=y ++CONFIG_BLK_CGROUP=y ++CONFIG_CFS_BANDWIDTH=y ++CONFIG_CGROUP_PIDS=y ++CONFIG_CGROUP_RDMA=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_HUGETLB=y ++CONFIG_CPUSETS=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_CGROUP_PERF=y ++CONFIG_CGROUP_BPF=y ++CONFIG_NAMESPACES=y ++CONFIG_USER_NS=y ++CONFIG_CHECKPOINT_RESTORE=y ++CONFIG_SCHED_AUTOGROUP=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_EXPERT=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_BPF_SYSCALL=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB_FREELIST_RANDOM=y ++CONFIG_PROFILING=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_ARM64_VA_BITS_48=y ++CONFIG_SCHED_MC=y ++CONFIG_SCHED_SMT=y ++CONFIG_NR_CPUS=8 ++CONFIG_HZ_100=y ++CONFIG_SECCOMP=y ++CONFIG_PARAVIRT_TIME_ACCOUNTING=y ++CONFIG_KEXEC=y ++CONFIG_KEXEC_FILE=y ++CONFIG_COMPAT=y ++# CONFIG_ARM64_PTR_AUTH is not set ++CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y ++CONFIG_CMDLINE="console=ttyAMA0" ++CONFIG_HIBERNATION=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_ENERGY_MODEL=y ++CONFIG_CPU_IDLE_GOV_LADDER=y ++CONFIG_ARM_CPUIDLE=y ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_CPUFREQ_DT=y ++CONFIG_ACPI_CPPC_CPUFREQ=y ++CONFIG_ARM_SCPI_CPUFREQ=y ++CONFIG_ARM_SCPI_PROTOCOL=y ++CONFIG_DMI_SYSFS=y ++CONFIG_ROCKCHIP_SIP=y ++CONFIG_EFI_VARS=y ++CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y ++# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set ++CONFIG_EFI_BOOTLOADER_CONTROL=y ++CONFIG_ACPI=y ++CONFIG_ACPI_EC_DEBUGFS=y ++CONFIG_ACPI_DOCK=y ++CONFIG_ACPI_IPMI=m ++CONFIG_ACPI_PCI_SLOT=y ++CONFIG_ACPI_HED=y ++CONFIG_ACPI_CUSTOM_METHOD=y ++CONFIG_PMIC_OPREGION=y ++CONFIG_ACPI_CONFIGFS=m ++CONFIG_VIRTUALIZATION=y ++CONFIG_KVM=y ++CONFIG_CRYPTO_SHA1_ARM64_CE=y ++CONFIG_CRYPTO_SHA2_ARM64_CE=y ++CONFIG_CRYPTO_SHA512_ARM64_CE=y ++CONFIG_CRYPTO_SHA3_ARM64=y ++CONFIG_CRYPTO_SM3_ARM64_CE=y ++CONFIG_CRYPTO_SM4_ARM64_CE=y ++CONFIG_CRYPTO_GHASH_ARM64_CE=y ++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y ++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y ++CONFIG_CRYPTO_AES_ARM64_CE_BLK=y ++CONFIG_CRYPTO_CHACHA20_NEON=y ++CONFIG_CRYPTO_NHPOLY1305_NEON=y ++CONFIG_CRYPTO_AES_ARM64_BS=y ++CONFIG_JUMP_LABEL=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_COMPRESS=y ++CONFIG_UNUSED_SYMBOLS=y ++CONFIG_BLK_DEV_ZONED=y ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_BLK_CMDLINE_PARSER=y ++CONFIG_BLK_WBT=y ++CONFIG_BLK_SED_OPAL=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_AIX_PARTITION=y ++CONFIG_OSF_PARTITION=y ++CONFIG_AMIGA_PARTITION=y ++CONFIG_MAC_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++CONFIG_MINIX_SUBPARTITION=y ++CONFIG_SOLARIS_X86_PARTITION=y ++CONFIG_UNIXWARE_DISKLABEL=y ++CONFIG_LDM_PARTITION=y ++CONFIG_SGI_PARTITION=y ++CONFIG_SUN_PARTITION=y ++CONFIG_KARMA_PARTITION=y ++CONFIG_IOSCHED_BFQ=y ++CONFIG_BFQ_GROUP_IOSCHED=y ++CONFIG_BINFMT_MISC=y ++CONFIG_KSM=y ++CONFIG_CLEANCACHE=y ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_ZSWAP=y ++CONFIG_Z3FOLD=y ++CONFIG_ZSMALLOC=y ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_PACKET_DIAG=m ++CONFIG_UNIX=y ++CONFIG_UNIX_DIAG=m ++CONFIG_TLS=m ++CONFIG_XFRM_USER=y ++CONFIG_XFRM_SUB_POLICY=y ++CONFIG_XFRM_STATISTICS=y ++CONFIG_NET_KEY=m ++CONFIG_NET_KEY_MIGRATE=y ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_FIB_TRIE_STATS=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_NET_IPGRE_BROADCAST=y ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_NET_IPVTI=m ++CONFIG_NET_FOU_IP_TUNNELS=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_DIAG=m ++CONFIG_INET_UDP_DIAG=m ++CONFIG_INET_RAW_DIAG=m ++CONFIG_TCP_CONG_ADVANCED=y ++CONFIG_TCP_CONG_HSTCP=m ++CONFIG_TCP_CONG_HYBLA=m ++CONFIG_TCP_CONG_NV=m ++CONFIG_TCP_CONG_SCALABLE=m ++CONFIG_TCP_CONG_LP=m ++CONFIG_TCP_CONG_VENO=m ++CONFIG_TCP_CONG_YEAH=m ++CONFIG_TCP_CONG_ILLINOIS=m ++CONFIG_TCP_CONG_DCTCP=m ++CONFIG_TCP_CONG_CDG=m ++CONFIG_TCP_CONG_BBR=m ++CONFIG_TCP_MD5SIG=y ++CONFIG_IPV6_ROUTER_PREF=y ++CONFIG_IPV6_ROUTE_INFO=y ++CONFIG_IPV6_OPTIMISTIC_DAD=y ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_MIP6=y ++CONFIG_IPV6_ILA=m ++CONFIG_IPV6_VTI=m ++CONFIG_IPV6_SIT=m ++CONFIG_IPV6_SIT_6RD=y ++CONFIG_IPV6_GRE=m ++CONFIG_IPV6_SUBTREES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y ++CONFIG_IPV6_SEG6_LWTUNNEL=y ++CONFIG_IPV6_SEG6_HMAC=y ++CONFIG_NETLABEL=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_LOG_NETDEV=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMEOUT=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NF_CT_NETLINK_TIMEOUT=m ++CONFIG_NF_CT_NETLINK_HELPER=m ++CONFIG_NETFILTER_NETLINK_GLUE_CT=y ++CONFIG_NF_TABLES=m ++CONFIG_NF_TABLES_INET=y ++CONFIG_NF_TABLES_NETDEV=y ++CONFIG_NFT_NUMGEN=m ++CONFIG_NFT_CT=m ++CONFIG_NFT_FLOW_OFFLOAD=m ++CONFIG_NFT_COUNTER=m ++CONFIG_NFT_CONNLIMIT=m ++CONFIG_NFT_LOG=m ++CONFIG_NFT_LIMIT=m ++CONFIG_NFT_MASQ=m ++CONFIG_NFT_REDIR=m ++CONFIG_NFT_NAT=m ++CONFIG_NFT_TUNNEL=m ++CONFIG_NFT_OBJREF=m ++CONFIG_NFT_QUEUE=m ++CONFIG_NFT_QUOTA=m ++CONFIG_NFT_REJECT=m ++CONFIG_NFT_COMPAT=m ++CONFIG_NFT_HASH=m ++CONFIG_NFT_FIB_INET=m ++CONFIG_NFT_XFRM=m ++CONFIG_NFT_SOCKET=m ++CONFIG_NFT_OSF=m ++CONFIG_NFT_TPROXY=m ++CONFIG_NFT_DUP_NETDEV=m ++CONFIG_NFT_FWD_NETDEV=m ++CONFIG_NFT_FIB_NETDEV=m ++CONFIG_NF_FLOW_TABLE_INET=m ++CONFIG_NF_FLOW_TABLE=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_CT=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CGROUP=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPCOMP=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPMARK=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_IPMAC=m ++CONFIG_IP_SET_HASH_MAC=m ++CONFIG_IP_SET_HASH_NETPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETNET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_IPV6=y ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_FO=m ++CONFIG_IP_VS_OVF=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_MH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NFT_DUP_IPV4=m ++CONFIG_NFT_FIB_IPV4=m ++CONFIG_NF_TABLES_ARP=y ++CONFIG_NF_FLOW_TABLE_IPV4=m ++CONFIG_NF_LOG_ARP=m ++CONFIG_NF_REJECT_IPV4=y ++CONFIG_IP_NF_IPTABLES=y ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_RPFILTER=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_SYNPROXY=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_CLUSTERIP=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_SECURITY=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NFT_DUP_IPV6=m ++CONFIG_NFT_FIB_IPV6=m ++CONFIG_NF_FLOW_TABLE_IPV6=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RPFILTER=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_MATCH_SRH=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_TARGET_SYNPROXY=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_SECURITY=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_NF_TABLES_BRIDGE=m ++CONFIG_NFT_BRIDGE_REJECT=m ++CONFIG_NF_LOG_BRIDGE=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_BPFILTER=y ++CONFIG_IP_DCCP=m ++CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y ++CONFIG_SCTP_COOKIE_HMAC_MD5=y ++CONFIG_RDS=m ++CONFIG_RDS_TCP=m ++CONFIG_TIPC=m ++CONFIG_ATM=m ++CONFIG_ATM_CLIP=m ++CONFIG_ATM_LANE=m ++CONFIG_ATM_BR2684=m ++CONFIG_L2TP=m ++CONFIG_L2TP_DEBUGFS=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_BRIDGE_VLAN_FILTERING=y ++CONFIG_NET_DSA=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_VLAN_8021Q_MVRP=y ++CONFIG_ATALK=m ++CONFIG_DEV_APPLETALK=m ++CONFIG_IPDDP=m ++CONFIG_IPDDP_ENCAP=y ++CONFIG_6LOWPAN=m ++CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m ++CONFIG_6LOWPAN_GHC_UDP=m ++CONFIG_6LOWPAN_GHC_ICMPV6=m ++CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m ++CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m ++CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_ATM=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_CBS=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=y ++CONFIG_NET_SCH_FQ=m ++CONFIG_NET_SCH_HHF=m ++CONFIG_NET_SCH_PIE=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_PERF=y ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=y ++CONFIG_NET_CLS_BPF=m ++CONFIG_NET_CLS_FLOWER=m ++CONFIG_NET_CLS_MATCHALL=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_CANID=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_EMATCH_IPT=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_SAMPLE=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_NET_ACT_VLAN=m ++CONFIG_NET_ACT_BPF=m ++CONFIG_NET_ACT_CONNMARK=m ++CONFIG_NET_ACT_SKBMOD=m ++CONFIG_NET_ACT_IFE=m ++CONFIG_NET_ACT_TUNNEL_KEY=m ++CONFIG_NET_IFE_SKBMARK=m ++CONFIG_NET_IFE_SKBPRIO=m ++CONFIG_NET_IFE_SKBTCINDEX=m ++CONFIG_DCB=y ++CONFIG_BATMAN_ADV=m ++# CONFIG_BATMAN_ADV_BATMAN_V is not set ++CONFIG_BATMAN_ADV_NC=y ++CONFIG_BATMAN_ADV_DEBUGFS=y ++CONFIG_OPENVSWITCH=m ++CONFIG_VSOCKETS=m ++CONFIG_VIRTIO_VSOCKETS=m ++CONFIG_NETLINK_DIAG=m ++CONFIG_MPLS_ROUTING=m ++CONFIG_CGROUP_NET_PRIO=y ++CONFIG_BPF_JIT=y ++CONFIG_BPF_STREAM_PARSER=y ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_VXCAN=m ++CONFIG_CAN_SLCAN=m ++CONFIG_CAN_C_CAN=m ++CONFIG_CAN_C_CAN_PLATFORM=m ++CONFIG_CAN_C_CAN_PCI=m ++CONFIG_CAN_CC770=m ++CONFIG_CAN_CC770_PLATFORM=m ++CONFIG_CAN_M_CAN=m ++CONFIG_CAN_SJA1000=m ++CONFIG_CAN_EMS_PCI=m ++CONFIG_CAN_KVASER_PCI=m ++CONFIG_CAN_PEAK_PCI=m ++CONFIG_CAN_PLX_PCI=m ++CONFIG_CAN_SJA1000_PLATFORM=m ++CONFIG_CAN_SOFTING=m ++CONFIG_CAN_8DEV_USB=m ++CONFIG_CAN_EMS_USB=m ++CONFIG_CAN_ESD_USB2=m ++CONFIG_CAN_GS_USB=m ++CONFIG_CAN_KVASER_USB=m ++CONFIG_CAN_PEAK_USB=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBTSDIO=m ++CONFIG_BT_HCIUART=m ++CONFIG_BT_HCIUART_BCSP=y ++CONFIG_BT_HCIUART_ATH3K=y ++CONFIG_BT_HCIUART_LL=y ++CONFIG_BT_HCIUART_3WIRE=y ++CONFIG_BT_HCIUART_INTEL=y ++CONFIG_BT_HCIUART_BCM=y ++CONFIG_BT_HCIUART_QCA=y ++CONFIG_BT_HCIUART_MRVL=y ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_CFG80211=m ++CONFIG_CFG80211_CERTIFICATION_ONUS=y ++# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set ++CONFIG_CFG80211_DEBUGFS=y ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_RFKILL_GPIO=m ++CONFIG_NET_9P=m ++CONFIG_NET_9P_VIRTIO=m ++CONFIG_NFC=m ++CONFIG_NFC_DIGITAL=m ++CONFIG_NFC_NCI=m ++CONFIG_NFC_HCI=m ++CONFIG_NFC_SHDLC=y ++CONFIG_NFC_SIM=m ++CONFIG_NFC_PORT100=m ++CONFIG_NFC_PN544_I2C=m ++CONFIG_NFC_MICROREAD_I2C=m ++CONFIG_NFC_MRVL_USB=m ++CONFIG_NFC_ST21NFCA_I2C=m ++CONFIG_PCI=y ++CONFIG_PCIEPORTBUS=y ++CONFIG_HOTPLUG_PCI_PCIE=y ++CONFIG_PCIEAER_INJECT=m ++CONFIG_PCIE_ECRC=y ++CONFIG_PCI_STUB=y ++CONFIG_PCI_IOV=y ++CONFIG_PCI_PRI=y ++CONFIG_PCI_PASID=y ++CONFIG_HOTPLUG_PCI=y ++CONFIG_HOTPLUG_PCI_ACPI=y ++CONFIG_PCI_HOST_GENERIC=y ++CONFIG_PCI_XGENE=y ++CONFIG_PCIE_ROCKCHIP_HOST=y ++CONFIG_PCIE_DW_PLAT_HOST=y ++CONFIG_PCI_HISI=y ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DEBUG_DEVRES=y ++CONFIG_SIMPLE_PM_BUS=y ++CONFIG_VEXPRESS_CONFIG=y ++CONFIG_CONNECTOR=y ++CONFIG_MTD=y ++CONFIG_MTD_OF_PARTS=m ++CONFIG_MTD_BLOCK=m ++CONFIG_MTD_CFI=m ++CONFIG_MTD_CFI_INTELEXT=m ++CONFIG_MTD_CFI_AMDSTD=m ++CONFIG_MTD_CFI_STAA=m ++CONFIG_MTD_PHYSMAP=m ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_RAW_NAND=y ++CONFIG_MTD_SPI_NOR=y ++CONFIG_MTD_UBI=m ++CONFIG_BLK_DEV_NULL_BLK=m ++CONFIG_ZRAM=m ++CONFIG_BLK_DEV_UMEM=m ++CONFIG_BLK_DEV_LOOP=m ++CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_SKD=m ++CONFIG_BLK_DEV_SX8=m ++CONFIG_BLK_DEV_RAM=m ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_ATA_OVER_ETH=m ++CONFIG_VIRTIO_BLK=m ++CONFIG_BLK_DEV_RBD=m ++CONFIG_BLK_DEV_NVME=m ++CONFIG_NVME_MULTIPATH=y ++CONFIG_TIFM_7XX1=m ++CONFIG_ENCLOSURE_SERVICES=m ++CONFIG_APDS9802ALS=m ++CONFIG_ISL29003=m ++CONFIG_ISL29020=m ++CONFIG_SENSORS_TSL2550=m ++CONFIG_SENSORS_BH1770=m ++CONFIG_SENSORS_APDS990X=m ++CONFIG_SRAM=y ++CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_LEGACY=m ++CONFIG_EEPROM_MAX6875=m ++CONFIG_SENSORS_LIS3_I2C=m ++CONFIG_ECHO=m ++CONFIG_RAID_ATTRS=m ++CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_BLK_DEV_SR=y ++CONFIG_CHR_DEV_SG=y ++CONFIG_CHR_DEV_SCH=m ++CONFIG_SCSI_ENCLOSURE=m ++CONFIG_SCSI_CONSTANTS=y ++CONFIG_SCSI_LOGGING=y ++CONFIG_SCSI_SCAN_ASYNC=y ++CONFIG_SCSI_FC_ATTRS=m ++CONFIG_SCSI_SAS_ATA=y ++CONFIG_SCSI_SRP_ATTRS=m ++CONFIG_ISCSI_TCP=m ++CONFIG_SCSI_BNX2_ISCSI=m ++CONFIG_SCSI_BNX2X_FCOE=m ++CONFIG_BE2ISCSI=m ++CONFIG_SCSI_HPSA=m ++CONFIG_SCSI_MVSAS=m ++# CONFIG_SCSI_MVSAS_DEBUG is not set ++CONFIG_SCSI_MVSAS_TASKLET=y ++CONFIG_SCSI_MVUMI=m ++CONFIG_SCSI_ARCMSR=m ++CONFIG_SCSI_ESAS2R=m ++CONFIG_MEGARAID_NEWGEN=y ++CONFIG_MEGARAID_MM=m ++CONFIG_MEGARAID_MAILBOX=m ++CONFIG_MEGARAID_LEGACY=m ++CONFIG_MEGARAID_SAS=m ++CONFIG_SCSI_UFSHCD=y ++CONFIG_SCSI_UFSHCD_PCI=m ++CONFIG_SCSI_UFSHCD_PLATFORM=y ++CONFIG_SCSI_HPTIOP=m ++CONFIG_LIBFC=m ++CONFIG_LIBFCOE=m ++CONFIG_FCOE=m ++CONFIG_SCSI_SNIC=m ++CONFIG_SCSI_DMX3191D=m ++CONFIG_SCSI_INITIO=m ++CONFIG_SCSI_INIA100=m ++CONFIG_SCSI_STEX=m ++CONFIG_SCSI_SYM53C8XX_2=m ++CONFIG_SCSI_IPR=m ++CONFIG_SCSI_QLOGIC_1280=m ++CONFIG_SCSI_QLA_FC=m ++CONFIG_TCM_QLA2XXX=m ++CONFIG_SCSI_QLA_ISCSI=m ++CONFIG_SCSI_DC395x=m ++CONFIG_SCSI_AM53C974=m ++CONFIG_SCSI_WD719X=m ++CONFIG_SCSI_DEBUG=m ++CONFIG_SCSI_PMCRAID=m ++CONFIG_SCSI_VIRTIO=y ++CONFIG_SCSI_CHELSIO_FCOE=m ++CONFIG_SCSI_DH=y ++CONFIG_SCSI_DH_RDAC=m ++CONFIG_SCSI_DH_HP_SW=m ++CONFIG_SCSI_DH_EMC=m ++CONFIG_SCSI_DH_ALUA=m ++CONFIG_ATA=y ++CONFIG_SATA_AHCI=y ++CONFIG_SATA_AHCI_PLATFORM=y ++CONFIG_AHCI_XGENE=y ++CONFIG_SATA_INIC162X=m ++CONFIG_SATA_ACARD_AHCI=m ++CONFIG_SATA_SIL24=y ++CONFIG_PDC_ADMA=m ++CONFIG_SATA_QSTOR=m ++CONFIG_SATA_SX4=m ++CONFIG_ATA_PIIX=y ++CONFIG_SATA_MV=m ++CONFIG_SATA_NV=m ++CONFIG_SATA_PROMISE=m ++CONFIG_SATA_SIL=m ++CONFIG_SATA_SIS=m ++CONFIG_SATA_SVW=m ++CONFIG_SATA_ULI=m ++CONFIG_SATA_VIA=m ++CONFIG_SATA_VITESSE=m ++CONFIG_PATA_ALI=m ++CONFIG_PATA_AMD=m ++CONFIG_PATA_ARTOP=m ++CONFIG_PATA_ATIIXP=m ++CONFIG_PATA_ATP867X=m ++CONFIG_PATA_CMD64X=m ++CONFIG_PATA_CYPRESS=m ++CONFIG_PATA_EFAR=m ++CONFIG_PATA_HPT366=m ++CONFIG_PATA_HPT37X=m ++CONFIG_PATA_HPT3X2N=m ++CONFIG_PATA_HPT3X3=m ++CONFIG_PATA_IT8213=m ++CONFIG_PATA_IT821X=m ++CONFIG_PATA_JMICRON=m ++CONFIG_PATA_MARVELL=m ++CONFIG_PATA_NETCELL=m ++CONFIG_PATA_NINJA32=m ++CONFIG_PATA_NS87415=m ++CONFIG_PATA_OLDPIIX=m ++CONFIG_PATA_OPTIDMA=m ++CONFIG_PATA_PDC2027X=m ++CONFIG_PATA_PDC_OLD=m ++CONFIG_PATA_RDC=m ++CONFIG_PATA_SCH=m ++CONFIG_PATA_SERVERWORKS=m ++CONFIG_PATA_SIL680=m ++CONFIG_PATA_TOSHIBA=m ++CONFIG_PATA_TRIFLEX=m ++CONFIG_PATA_VIA=m ++CONFIG_PATA_WINBOND=m ++CONFIG_PATA_CMD640_PCI=m ++CONFIG_PATA_MPIIX=m ++CONFIG_PATA_NS87410=m ++CONFIG_PATA_OPTI=m ++CONFIG_PATA_PLATFORM=y ++CONFIG_PATA_OF_PLATFORM=y ++CONFIG_ATA_GENERIC=m ++CONFIG_MD=y ++CONFIG_BLK_DEV_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_MD_MULTIPATH=m ++CONFIG_MD_FAULTY=m ++CONFIG_MD_CLUSTER=m ++CONFIG_BCACHE=m ++CONFIG_BLK_DEV_DM=y ++CONFIG_DM_DEBUG=y ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=y ++CONFIG_DM_THIN_PROVISIONING=m ++CONFIG_DM_CACHE=m ++CONFIG_DM_WRITECACHE=m ++CONFIG_DM_MIRROR=y ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=y ++CONFIG_DM_MULTIPATH=m ++CONFIG_DM_MULTIPATH_QL=m ++CONFIG_DM_MULTIPATH_ST=m ++CONFIG_DM_DELAY=m ++CONFIG_DM_DUST=m ++CONFIG_DM_INIT=y ++CONFIG_DM_UEVENT=y ++CONFIG_DM_FLAKEY=m ++CONFIG_DM_VERITY=m ++CONFIG_DM_VERITY_FEC=y ++CONFIG_DM_SWITCH=m ++CONFIG_DM_LOG_WRITES=m ++CONFIG_DM_INTEGRITY=m ++CONFIG_DM_ZONED=m ++CONFIG_TARGET_CORE=m ++CONFIG_TCM_IBLOCK=m ++CONFIG_TCM_FILEIO=m ++CONFIG_TCM_PSCSI=m ++CONFIG_TCM_USER2=m ++CONFIG_LOOPBACK_TARGET=m ++CONFIG_TCM_FC=m ++CONFIG_ISCSI_TARGET=m ++CONFIG_FIREWIRE_NOSY=m ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_WIREGUARD=m ++CONFIG_EQUALIZER=m ++CONFIG_NET_FC=y ++CONFIG_IFB=m ++CONFIG_NET_TEAM=m ++CONFIG_NET_TEAM_MODE_BROADCAST=m ++CONFIG_NET_TEAM_MODE_ROUNDROBIN=m ++CONFIG_NET_TEAM_MODE_RANDOM=m ++CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m ++CONFIG_NET_TEAM_MODE_LOADBALANCE=m ++CONFIG_MACVLAN=m ++CONFIG_MACVTAP=m ++CONFIG_IPVLAN=m ++CONFIG_IPVTAP=m ++CONFIG_VXLAN=m ++CONFIG_GENEVE=m ++CONFIG_NETCONSOLE=m ++CONFIG_NETCONSOLE_DYNAMIC=y ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_VIRTIO_NET=m ++CONFIG_NLMON=m ++CONFIG_NET_VRF=m ++# CONFIG_ATM_DRIVERS is not set ++CONFIG_NET_DSA_BCM_SF2=m ++CONFIG_NET_DSA_MV88E6060=m ++CONFIG_NET_DSA_MV88E6XXX=m ++CONFIG_NET_DSA_MV88E6XXX_PTP=y ++CONFIG_NET_DSA_QCA8K=m ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_ADAPTEC is not set ++CONFIG_ET131X=m ++CONFIG_ACENIC=m ++CONFIG_ALTERA_TSE=m ++CONFIG_AMD8111_ETH=m ++CONFIG_PCNET32=m ++CONFIG_AMD_XGBE=m ++CONFIG_AQTION=m ++CONFIG_ATL2=m ++CONFIG_ATL1=m ++CONFIG_ATL1E=m ++CONFIG_ATL1C=m ++CONFIG_ALX=m ++# CONFIG_NET_VENDOR_AURORA is not set ++CONFIG_B44=m ++CONFIG_BCMGENET=m ++CONFIG_TIGON3=m ++CONFIG_BNX2X=m ++# CONFIG_NET_VENDOR_BROCADE is not set ++CONFIG_MACB=m ++# CONFIG_NET_VENDOR_CAVIUM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CISCO is not set ++CONFIG_DNET=m ++# CONFIG_NET_VENDOR_DEC is not set ++CONFIG_DL2K=m ++CONFIG_SUNDANCE=m ++# CONFIG_NET_VENDOR_EMULEX is not set ++# CONFIG_NET_VENDOR_EZCHIP is not set ++CONFIG_HIX5HD2_GMAC=m ++CONFIG_HIP04_ETH=m ++CONFIG_HNS_DSAF=m ++CONFIG_HNS_ENET=m ++# CONFIG_NET_VENDOR_I825XX is not set ++CONFIG_E100=m ++CONFIG_E1000=m ++CONFIG_E1000E=m ++CONFIG_IGB=m ++CONFIG_IGBVF=m ++CONFIG_IXGB=m ++CONFIG_IXGBE=m ++CONFIG_IXGBE_DCB=y ++CONFIG_IXGBEVF=m ++CONFIG_I40E=m ++CONFIG_I40EVF=m ++CONFIG_FM10K=m ++CONFIG_JME=m ++CONFIG_MVMDIO=m ++CONFIG_SKGE=m ++CONFIG_SKGE_GENESIS=y ++CONFIG_SKY2=m ++CONFIG_MLX4_EN=m ++CONFIG_KSZ884X_PCI=m ++CONFIG_MYRI10GE=m ++CONFIG_FEALNX=m ++CONFIG_NATSEMI=m ++CONFIG_NS83820=m ++CONFIG_NE2K_PCI=m ++CONFIG_FORCEDETH=m ++CONFIG_ETHOC=m ++CONFIG_HAMACHI=m ++CONFIG_YELLOWFIN=m ++# CONFIG_NET_VENDOR_QLOGIC is not set ++# CONFIG_NET_VENDOR_QUALCOMM is not set ++CONFIG_R6040=m ++CONFIG_8139CP=m ++CONFIG_8139TOO=m ++# CONFIG_8139TOO_PIO is not set ++CONFIG_8139TOO_8129=y ++CONFIG_R8169=m ++# CONFIG_NET_VENDOR_RENESAS is not set ++CONFIG_ROCKER=m ++# CONFIG_NET_VENDOR_SAMSUNG is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++CONFIG_SC92031=m ++CONFIG_SIS900=m ++CONFIG_SIS190=m ++CONFIG_SMC91X=m ++CONFIG_EPIC100=m ++CONFIG_SMSC911X=m ++CONFIG_SMSC9420=m ++CONFIG_STMMAC_ETH=m ++CONFIG_DWMAC_DWC_QOS_ETH=m ++# CONFIG_NET_VENDOR_SUN is not set ++CONFIG_TEHUTI=m ++CONFIG_VIA_RHINE=m ++CONFIG_VIA_RHINE_MMIO=y ++CONFIG_VIA_VELOCITY=m ++# CONFIG_NET_VENDOR_WIZNET is not set ++CONFIG_NET_SB1000=y ++CONFIG_MDIO_BITBANG=m ++CONFIG_MDIO_BUS_MUX_GPIO=m ++CONFIG_MDIO_BUS_MUX_MMIOREG=m ++CONFIG_PHYLIB=y ++CONFIG_LED_TRIGGER_PHY=y ++CONFIG_SFP=m ++CONFIG_AMD_PHY=m ++CONFIG_BCM87XX_PHY=m ++CONFIG_BROADCOM_PHY=m ++CONFIG_CICADA_PHY=m ++CONFIG_DAVICOM_PHY=m ++CONFIG_DP83848_PHY=m ++CONFIG_DP83867_PHY=m ++CONFIG_ICPLUS_PHY=m ++CONFIG_LSI_ET1011C_PHY=m ++CONFIG_LXT_PHY=m ++CONFIG_MARVELL_10G_PHY=m ++CONFIG_MICREL_PHY=m ++CONFIG_NATIONAL_PHY=m ++CONFIG_AT803X_PHY=m ++CONFIG_QSEMI_PHY=m ++CONFIG_ROCKCHIP_PHY=y ++CONFIG_STE10XP=m ++CONFIG_VITESSE_PHY=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPTP=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m ++CONFIG_USB_LAN78XX=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=m ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_USB_NET_CH9200=m ++CONFIG_ADM8211=m ++CONFIG_ATH5K=m ++CONFIG_ATH5K_DEBUG=y ++CONFIG_ATH9K=m ++CONFIG_ATH9K_AHB=y ++CONFIG_ATH9K_DEBUGFS=y ++CONFIG_ATH9K_HTC=m ++CONFIG_ATH9K_HWRNG=y ++CONFIG_ATH9K_COMMON_SPECTRAL=y ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_SDIO=m ++CONFIG_ATH6KL_USB=m ++CONFIG_ATH6KL_DEBUG=y ++CONFIG_AR5523=m ++CONFIG_WIL6210=m ++CONFIG_ATH10K=m ++CONFIG_ATH10K_PCI=m ++CONFIG_ATH10K_DEBUGFS=y ++CONFIG_WCN36XX=m ++CONFIG_ATMEL=m ++CONFIG_PCI_ATMEL=m ++CONFIG_AT76C50X_USB=m ++CONFIG_B43=m ++CONFIG_B43_SDIO=y ++CONFIG_B43_DEBUG=y ++CONFIG_B43LEGACY=m ++CONFIG_BRCMSMAC=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_BRCMFMAC_PCIE=y ++CONFIG_BRCM_TRACING=y ++CONFIG_BRCMDBG=y ++CONFIG_IPW2100=m ++CONFIG_IPW2100_MONITOR=y ++CONFIG_IPW2200=m ++CONFIG_IPW2200_MONITOR=y ++CONFIG_IPW2200_PROMISCUOUS=y ++CONFIG_IPW2200_QOS=y ++CONFIG_IWL4965=m ++CONFIG_IWL3945=m ++CONFIG_IWLEGACY_DEBUG=y ++CONFIG_IWLEGACY_DEBUGFS=y ++CONFIG_IWLWIFI=m ++CONFIG_IWLDVM=m ++CONFIG_IWLMVM=m ++CONFIG_IWLWIFI_DEBUG=y ++CONFIG_IWLWIFI_DEBUGFS=y ++CONFIG_HOSTAP=m ++CONFIG_HOSTAP_FIRMWARE=y ++CONFIG_HOSTAP_PLX=m ++CONFIG_HOSTAP_PCI=m ++CONFIG_HERMES=m ++CONFIG_HERMES_PRISM=y ++CONFIG_PLX_HERMES=m ++CONFIG_TMD_HERMES=m ++CONFIG_NORTEL_HERMES=m ++CONFIG_PCI_HERMES=m ++CONFIG_ORINOCO_USB=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_P54_PCI=m ++CONFIG_PRISM54=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_LIBERTAS_MESH=y ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_MWIFIEX_PCIE=m ++CONFIG_MWIFIEX_USB=m ++CONFIG_MWL8K=m ++CONFIG_MT7601U=m ++CONFIG_RT2X00=m ++CONFIG_RT2400PCI=m ++CONFIG_RT2500PCI=m ++CONFIG_RT61PCI=m ++CONFIG_RT2800PCI=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_RT2X00_LIB_DEBUGFS=y ++CONFIG_RTL8180=m ++CONFIG_RTL8187=m ++CONFIG_RTL8192CE=m ++CONFIG_RTL8192SE=m ++CONFIG_RTL8192DE=m ++CONFIG_RTL8723AE=m ++CONFIG_RTL8723BE=m ++CONFIG_RTL8188EE=m ++CONFIG_RTL8192EE=m ++CONFIG_RTL8821AE=m ++CONFIG_RTL8192CU=m ++CONFIG_RTL8XXXU=m ++CONFIG_RSI_91X=m ++CONFIG_CW1200=m ++CONFIG_CW1200_WLAN_SDIO=m ++CONFIG_WL1251=m ++CONFIG_WL1251_SPI=m ++CONFIG_WL1251_SDIO=m ++CONFIG_WL12XX=m ++CONFIG_WL18XX=m ++CONFIG_WLCORE_SPI=m ++CONFIG_WLCORE_SDIO=m ++CONFIG_USB_ZD1201=m ++CONFIG_ZD1211RW=m ++CONFIG_QTNFMAC_PCIE=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_IEEE802154_FAKELB=m ++CONFIG_IEEE802154_ATUSB=m ++CONFIG_INPUT_SPARSEKMAP=m ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=y ++CONFIG_KEYBOARD_ADC=m ++CONFIG_KEYBOARD_GPIO=m ++CONFIG_KEYBOARD_GPIO_POLLED=m ++CONFIG_KEYBOARD_CROS_EC=y ++CONFIG_MOUSE_PS2_ELANTECH=y ++CONFIG_MOUSE_PS2_SENTELIC=y ++CONFIG_MOUSE_SERIAL=m ++CONFIG_MOUSE_APPLETOUCH=m ++CONFIG_MOUSE_BCM5974=m ++CONFIG_MOUSE_CYAPA=m ++CONFIG_MOUSE_ELAN_I2C=y ++CONFIG_MOUSE_ELAN_I2C_SMBUS=y ++CONFIG_MOUSE_VSXXXAA=m ++CONFIG_MOUSE_SYNAPTICS_I2C=m ++CONFIG_MOUSE_SYNAPTICS_USB=m ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=m ++CONFIG_JOYSTICK_IFORCE_232=m ++CONFIG_JOYSTICK_WARRIOR=m ++CONFIG_JOYSTICK_MAGELLAN=m ++CONFIG_JOYSTICK_SPACEORB=m ++CONFIG_JOYSTICK_SPACEBALL=m ++CONFIG_JOYSTICK_STINGER=m ++CONFIG_JOYSTICK_TWIDJOY=m ++CONFIG_JOYSTICK_ZHENHUA=m ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_JOYSTICK_XPAD_LEDS=y ++CONFIG_INPUT_TABLET=y ++CONFIG_TABLET_USB_ACECAD=m ++CONFIG_TABLET_USB_AIPTEK=m ++CONFIG_TABLET_USB_GTCO=m ++CONFIG_TABLET_USB_HANWANG=m ++CONFIG_TABLET_USB_KBTAB=m ++CONFIG_TABLET_USB_PEGASUS=m ++CONFIG_TABLET_SERIAL_WACOM4=m ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ATMEL_MXT=y ++CONFIG_TOUCHSCREEN_AUO_PIXCIR=m ++CONFIG_TOUCHSCREEN_DYNAPRO=m ++CONFIG_TOUCHSCREEN_EETI=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_FUJITSU=m ++CONFIG_TOUCHSCREEN_ILI210X=m ++CONFIG_TOUCHSCREEN_GUNZE=m ++CONFIG_TOUCHSCREEN_ELAN=m ++CONFIG_TOUCHSCREEN_ELO=m ++CONFIG_TOUCHSCREEN_WACOM_W8001=m ++CONFIG_TOUCHSCREEN_WACOM_I2C=m ++CONFIG_TOUCHSCREEN_MCS5000=m ++CONFIG_TOUCHSCREEN_MMS114=m ++CONFIG_TOUCHSCREEN_MTOUCH=m ++CONFIG_TOUCHSCREEN_INEXIO=m ++CONFIG_TOUCHSCREEN_MK712=m ++CONFIG_TOUCHSCREEN_PENMOUNT=m ++CONFIG_TOUCHSCREEN_EDT_FT5X06=m ++CONFIG_TOUCHSCREEN_TOUCHRIGHT=m ++CONFIG_TOUCHSCREEN_TOUCHWIN=m ++CONFIG_TOUCHSCREEN_PIXCIR=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_TOUCHIT213=m ++CONFIG_TOUCHSCREEN_TSC_SERIO=m ++CONFIG_TOUCHSCREEN_TSC2007=m ++CONFIG_TOUCHSCREEN_ST1232=m ++CONFIG_TOUCHSCREEN_ZFORCE=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_E3X0_BUTTON=m ++CONFIG_INPUT_MMA8450=m ++CONFIG_INPUT_GP2A=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_KXTJ9=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_AXP20X_PEK=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_PWM_BEEPER=m ++CONFIG_INPUT_RK805_PWRKEY=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_INPUT_CMA3000_I2C=m ++CONFIG_SERIO_AMBAKMI=y ++CONFIG_SERIO_RAW=m ++CONFIG_SERIO_ALTERA_PS2=m ++CONFIG_SERIO_ARC_PS2=m ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set ++CONFIG_SERIAL_8250_CONSOLE=y ++CONFIG_SERIAL_8250_NR_UARTS=32 ++CONFIG_SERIAL_8250_EXTENDED=y ++CONFIG_SERIAL_8250_MANY_PORTS=y ++CONFIG_SERIAL_8250_SHARE_IRQ=y ++CONFIG_SERIAL_8250_RSA=y ++CONFIG_SERIAL_8250_DW=y ++CONFIG_SERIAL_OF_PLATFORM=y ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y ++CONFIG_SERIAL_JSM=m ++CONFIG_SERIAL_ARC=m ++CONFIG_SERIAL_FSL_LPUART=y ++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y ++CONFIG_SERIAL_NONSTANDARD=y ++CONFIG_ROCKETPORT=m ++CONFIG_CYCLADES=m ++CONFIG_SYNCLINKMP=m ++CONFIG_SYNCLINK_GT=m ++CONFIG_N_HDLC=m ++CONFIG_N_GSM=m ++CONFIG_NOZOMI=m ++CONFIG_SERIAL_DEV_BUS=y ++CONFIG_VIRTIO_CONSOLE=y ++CONFIG_IPMI_HANDLER=y ++CONFIG_IPMI_DEVICE_INTERFACE=m ++CONFIG_IPMI_SSIF=m ++CONFIG_IPMI_WATCHDOG=m ++CONFIG_IPMI_POWEROFF=m ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_TIMERIOMEM=m ++CONFIG_HW_RANDOM_VIRTIO=m ++CONFIG_RAW_DRIVER=y ++CONFIG_MAX_RAW_DEVS=8192 ++CONFIG_TCG_TPM=y ++CONFIG_TCG_TIS_I2C_INFINEON=y ++CONFIG_TCG_ATMEL=m ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_ARB_GPIO_CHALLENGE=m ++CONFIG_I2C_MUX_GPIO=m ++CONFIG_I2C_MUX_GPMUX=m ++CONFIG_I2C_MUX_PCA9541=m ++CONFIG_I2C_MUX_PCA954x=y ++CONFIG_I2C_MUX_PINCTRL=m ++CONFIG_I2C_MUX_REG=m ++CONFIG_I2C_DEMUX_PINCTRL=m ++CONFIG_I2C_NFORCE2=m ++CONFIG_I2C_SCMI=y ++CONFIG_I2C_DESIGNWARE_PLATFORM=y ++CONFIG_I2C_DESIGNWARE_PCI=m ++CONFIG_I2C_GPIO=m ++CONFIG_I2C_PCA_PLATFORM=m ++CONFIG_I2C_RK3X=y ++CONFIG_I2C_SIMTEC=m ++CONFIG_I2C_DIOLAN_U2C=m ++CONFIG_I2C_TINY_USB=m ++CONFIG_I2C_VIPERBOARD=m ++CONFIG_I2C_CROS_EC_TUNNEL=y ++CONFIG_I2C_STUB=m ++CONFIG_I2C_SLAVE=y ++CONFIG_I2C_SLAVE_EEPROM=m ++CONFIG_SPI=y ++CONFIG_SPI_NXP_FLEXSPI=y ++CONFIG_SPI_GPIO=y ++CONFIG_SPI_PL022=y ++CONFIG_SPI_ROCKCHIP=y ++CONFIG_SPI_SPIDEV=m ++CONFIG_SPMI=y ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m ++CONFIG_DP83640_PHY=m ++CONFIG_PINCTRL_AMD=y ++CONFIG_PINCTRL_SINGLE=y ++CONFIG_PINCTRL_MAX77620=y ++CONFIG_PINCTRL_RK805=y ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_DWAPB=y ++CONFIG_GPIO_PL061=y ++CONFIG_GPIO_SYSCON=y ++CONFIG_GPIO_XGENE=y ++CONFIG_GPIO_PCA953X=y ++CONFIG_GPIO_PCA953X_IRQ=y ++CONFIG_GPIO_MAX77620=y ++CONFIG_GPIO_VIPERBOARD=m ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++# CONFIG_W1_SLAVE_DS2408_READBACK is not set ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2433_CRC=y ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_POWER_AVS=y ++CONFIG_ROCKCHIP_IODOMAIN=y ++CONFIG_POWER_RESET_GPIO=y ++CONFIG_POWER_RESET_GPIO_RESTART=y ++CONFIG_POWER_RESET_RESTART=y ++CONFIG_POWER_RESET_VEXPRESS=y ++CONFIG_POWER_RESET_XGENE=y ++CONFIG_POWER_RESET_SYSCON=y ++CONFIG_POWER_RESET_SYSCON_POWEROFF=y ++CONFIG_SYSCON_REBOOT_MODE=y ++CONFIG_BATTERY_CW2015=m ++CONFIG_BATTERY_SBS=m ++CONFIG_CHARGER_SBS=m ++CONFIG_MANAGER_SBS=m ++CONFIG_CHARGER_AXP20X=m ++CONFIG_CHARGER_GPIO=y ++CONFIG_CHARGER_SMB347=m ++CONFIG_CHARGER_CROS_USBPD=m ++CONFIG_SENSORS_AD7414=m ++CONFIG_SENSORS_AD7418=m ++CONFIG_SENSORS_ADM1021=m ++CONFIG_SENSORS_ADM1025=m ++CONFIG_SENSORS_ADM1026=m ++CONFIG_SENSORS_ADM1029=m ++CONFIG_SENSORS_ADM1031=m ++CONFIG_SENSORS_ADM9240=m ++CONFIG_SENSORS_ADT7410=m ++CONFIG_SENSORS_ADT7411=m ++CONFIG_SENSORS_ADT7462=m ++CONFIG_SENSORS_ADT7470=m ++CONFIG_SENSORS_ADT7475=m ++CONFIG_SENSORS_ASC7621=m ++CONFIG_SENSORS_ARM_SCPI=y ++CONFIG_SENSORS_ATXP1=m ++CONFIG_SENSORS_DS620=m ++CONFIG_SENSORS_DS1621=m ++CONFIG_SENSORS_F71805F=m ++CONFIG_SENSORS_F71882FG=m ++CONFIG_SENSORS_F75375S=m ++CONFIG_SENSORS_GL518SM=m ++CONFIG_SENSORS_GL520SM=m ++CONFIG_SENSORS_G760A=m ++CONFIG_SENSORS_G762=m ++CONFIG_SENSORS_GPIO_FAN=m ++CONFIG_SENSORS_IBMAEM=m ++CONFIG_SENSORS_IBMPEX=m ++CONFIG_SENSORS_IIO_HWMON=m ++CONFIG_SENSORS_IT87=m ++CONFIG_SENSORS_POWR1220=m ++CONFIG_SENSORS_LINEAGE=m ++CONFIG_SENSORS_LTC2945=m ++CONFIG_SENSORS_LTC4151=m ++CONFIG_SENSORS_LTC4215=m ++CONFIG_SENSORS_LTC4222=m ++CONFIG_SENSORS_LTC4245=m ++CONFIG_SENSORS_LTC4260=m ++CONFIG_SENSORS_LTC4261=m ++CONFIG_SENSORS_MAX16065=m ++CONFIG_SENSORS_MAX1619=m ++CONFIG_SENSORS_MAX1668=m ++CONFIG_SENSORS_MAX197=m ++CONFIG_SENSORS_MAX6639=m ++CONFIG_SENSORS_MAX6642=m ++CONFIG_SENSORS_MAX6650=m ++CONFIG_SENSORS_MAX6697=m ++CONFIG_SENSORS_MCP3021=m ++CONFIG_SENSORS_LM63=m ++CONFIG_SENSORS_LM73=m ++CONFIG_SENSORS_LM75=m ++CONFIG_SENSORS_LM77=m ++CONFIG_SENSORS_LM78=m ++CONFIG_SENSORS_LM80=m ++CONFIG_SENSORS_LM83=m ++CONFIG_SENSORS_LM85=m ++CONFIG_SENSORS_LM87=m ++CONFIG_SENSORS_LM90=m ++CONFIG_SENSORS_LM92=m ++CONFIG_SENSORS_LM93=m ++CONFIG_SENSORS_LM95234=m ++CONFIG_SENSORS_LM95241=m ++CONFIG_SENSORS_LM95245=m ++CONFIG_SENSORS_PC87360=m ++CONFIG_SENSORS_PC87427=m ++CONFIG_SENSORS_NTC_THERMISTOR=m ++CONFIG_SENSORS_NCT6683=m ++CONFIG_SENSORS_NCT6775=m ++CONFIG_SENSORS_NCT7802=m ++CONFIG_SENSORS_NCT7904=m ++CONFIG_SENSORS_PCF8591=m ++CONFIG_PMBUS=m ++CONFIG_SENSORS_ADM1275=m ++CONFIG_SENSORS_LM25066=m ++CONFIG_SENSORS_LTC2978=m ++CONFIG_SENSORS_MAX16064=m ++CONFIG_SENSORS_MAX34440=m ++CONFIG_SENSORS_MAX8688=m ++CONFIG_SENSORS_TPS40422=m ++CONFIG_SENSORS_UCD9000=m ++CONFIG_SENSORS_UCD9200=m ++CONFIG_SENSORS_ZL6100=m ++CONFIG_SENSORS_PWM_FAN=m ++CONFIG_SENSORS_SHT15=m ++CONFIG_SENSORS_SHT21=m ++CONFIG_SENSORS_SHT3x=m ++CONFIG_SENSORS_SHTC1=m ++CONFIG_SENSORS_SIS5595=m ++CONFIG_SENSORS_DME1737=m ++CONFIG_SENSORS_EMC1403=m ++CONFIG_SENSORS_EMC6W201=m ++CONFIG_SENSORS_SMSC47M1=m ++CONFIG_SENSORS_SMSC47M192=m ++CONFIG_SENSORS_SMSC47B397=m ++CONFIG_SENSORS_SCH5627=m ++CONFIG_SENSORS_SCH5636=m ++CONFIG_SENSORS_ADC128D818=m ++CONFIG_SENSORS_ADS7828=m ++CONFIG_SENSORS_AMC6821=m ++CONFIG_SENSORS_INA209=m ++CONFIG_SENSORS_INA2XX=m ++CONFIG_SENSORS_INA3221=m ++CONFIG_SENSORS_TC74=m ++CONFIG_SENSORS_THMC50=m ++CONFIG_SENSORS_TMP102=m ++CONFIG_SENSORS_TMP103=m ++CONFIG_SENSORS_TMP108=m ++CONFIG_SENSORS_TMP401=m ++CONFIG_SENSORS_TMP421=m ++CONFIG_SENSORS_VEXPRESS=m ++CONFIG_SENSORS_VIA686A=m ++CONFIG_SENSORS_VT1211=m ++CONFIG_SENSORS_VT8231=m ++CONFIG_SENSORS_W83781D=m ++CONFIG_SENSORS_W83791D=m ++CONFIG_SENSORS_W83792D=m ++CONFIG_SENSORS_W83793=m ++CONFIG_SENSORS_W83795=m ++CONFIG_SENSORS_W83L785TS=m ++CONFIG_SENSORS_W83L786NG=m ++CONFIG_SENSORS_W83627HF=m ++CONFIG_SENSORS_W83627EHF=m ++CONFIG_SENSORS_ACPI_POWER=m ++CONFIG_THERMAL_WRITABLE_TRIPS=y ++CONFIG_THERMAL_GOV_FAIR_SHARE=y ++CONFIG_THERMAL_GOV_BANG_BANG=y ++CONFIG_THERMAL_GOV_USER_SPACE=y ++CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y ++CONFIG_CPU_THERMAL=y ++CONFIG_CLOCK_THERMAL=y ++CONFIG_DEVFREQ_THERMAL=y ++CONFIG_THERMAL_EMULATION=y ++CONFIG_MAX77620_THERMAL=m ++CONFIG_ROCKCHIP_THERMAL=m ++CONFIG_GENERIC_ADC_THERMAL=m ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_SOFT_WATCHDOG=m ++CONFIG_GPIO_WATCHDOG=m ++CONFIG_ARM_SP805_WATCHDOG=m ++CONFIG_ARM_SBSA_WATCHDOG=m ++CONFIG_DW_WATCHDOG=m ++CONFIG_MAX77620_WATCHDOG=m ++CONFIG_ALIM7101_WDT=m ++CONFIG_I6300ESB_WDT=m ++CONFIG_PCIPCWATCHDOG=m ++CONFIG_WDTPCI=m ++CONFIG_USBPCWATCHDOG=m ++CONFIG_SSB_DRIVER_GPIO=y ++CONFIG_BCMA_DRIVER_GMAC_CMN=y ++CONFIG_BCMA_DRIVER_GPIO=y ++CONFIG_MFD_AXP20X_I2C=y ++CONFIG_MFD_MAX77620=y ++CONFIG_MFD_VIPERBOARD=m ++CONFIG_MFD_RK808=y ++CONFIG_MFD_SEC_CORE=y ++CONFIG_MFD_SM501=m ++CONFIG_MFD_SM501_GPIO=y ++CONFIG_MFD_VX855=m ++CONFIG_REGULATOR_FIXED_VOLTAGE=y ++CONFIG_REGULATOR_AXP20X=y ++CONFIG_REGULATOR_FAN53555=y ++CONFIG_REGULATOR_GPIO=y ++CONFIG_REGULATOR_MAX77620=y ++CONFIG_REGULATOR_PFUZE100=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_QCOM_SPMI=y ++CONFIG_REGULATOR_RK808=y ++CONFIG_REGULATOR_S2MPS11=y ++CONFIG_REGULATOR_VCTRL=y ++CONFIG_REGULATOR_VEXPRESS=y ++CONFIG_RC_CORE=y ++CONFIG_LIRC=y ++CONFIG_BPF_LIRC_MODE2=y ++CONFIG_RC_DECODERS=y ++CONFIG_IR_NEC_DECODER=m ++CONFIG_IR_RC5_DECODER=m ++CONFIG_IR_RC6_DECODER=m ++CONFIG_IR_JVC_DECODER=m ++CONFIG_IR_SONY_DECODER=m ++CONFIG_IR_SANYO_DECODER=m ++CONFIG_IR_SHARP_DECODER=m ++CONFIG_IR_MCE_KBD_DECODER=m ++CONFIG_IR_XMP_DECODER=m ++CONFIG_IR_IMON_DECODER=m ++CONFIG_IR_RCMM_DECODER=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_ENE=m ++CONFIG_IR_HIX5HD2=m ++CONFIG_IR_IMON=m ++CONFIG_IR_IMON_RAW=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_ITE_CIR=m ++CONFIG_IR_FINTEK=m ++CONFIG_IR_NUVOTON=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_SPI=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGORPLUGUSB=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_IR_SERIAL=m ++CONFIG_IR_SERIAL_TRANSMITTER=y ++CONFIG_IR_SIR=m ++CONFIG_RC_XBOX_DVD=m ++CONFIG_MEDIA_SUPPORT=y ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_SDR_SUPPORT=y ++CONFIG_MEDIA_CEC_SUPPORT=y ++CONFIG_MEDIA_CEC_RC=y ++CONFIG_MEDIA_CONTROLLER_REQUEST_API=y ++CONFIG_VIDEO_V4L2_SUBDEV_API=y ++CONFIG_DVB_MAX_ADAPTERS=8 ++CONFIG_DVB_DYNAMIC_MINORS=y ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TOUPTEK=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_DVB_USB_ZD1301=m ++CONFIG_DVB_TTUSB_BUDGET=m ++CONFIG_DVB_TTUSB_DEC=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_AS102=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_USB_AIRSPY=m ++CONFIG_USB_HACKRF=m ++CONFIG_USB_PULSE8_CEC=m ++CONFIG_USB_RAINSHADOW_CEC=m ++CONFIG_MEDIA_PCI_SUPPORT=y ++CONFIG_VIDEO_SOLO6X10=m ++CONFIG_VIDEO_TW68=m ++CONFIG_VIDEO_IVTV=m ++CONFIG_VIDEO_IVTV_ALSA=m ++CONFIG_VIDEO_FB_IVTV=m ++CONFIG_VIDEO_HEXIUM_GEMINI=m ++CONFIG_VIDEO_HEXIUM_ORION=m ++CONFIG_VIDEO_MXB=m ++CONFIG_VIDEO_DT3155=m ++CONFIG_VIDEO_CX18=m ++CONFIG_VIDEO_CX18_ALSA=m ++CONFIG_VIDEO_CX23885=m ++CONFIG_MEDIA_ALTERA_CI=m ++CONFIG_VIDEO_CX25821=m ++CONFIG_VIDEO_CX25821_ALSA=m ++CONFIG_VIDEO_CX88=m ++CONFIG_VIDEO_CX88_ALSA=m ++CONFIG_VIDEO_CX88_BLACKBIRD=m ++CONFIG_VIDEO_CX88_DVB=m ++CONFIG_VIDEO_BT848=m ++CONFIG_DVB_BT8XX=m ++CONFIG_VIDEO_SAA7134=m ++CONFIG_VIDEO_SAA7134_ALSA=m ++CONFIG_VIDEO_SAA7134_DVB=m ++CONFIG_VIDEO_SAA7134_GO7007=m ++CONFIG_VIDEO_SAA7164=m ++CONFIG_DVB_AV7110=m ++CONFIG_DVB_BUDGET_CORE=m ++CONFIG_DVB_BUDGET=m ++CONFIG_DVB_BUDGET_CI=m ++CONFIG_DVB_BUDGET_AV=m ++CONFIG_DVB_BUDGET_PATCH=m ++CONFIG_DVB_B2C2_FLEXCOP_PCI=m ++CONFIG_DVB_PLUTO2=m ++CONFIG_DVB_DM1105=m ++CONFIG_DVB_PT1=m ++CONFIG_DVB_PT3=m ++CONFIG_MANTIS_CORE=m ++CONFIG_DVB_MANTIS=m ++CONFIG_DVB_HOPPER=m ++CONFIG_DVB_NGENE=m ++CONFIG_DVB_DDBRIDGE=m ++CONFIG_DVB_SMIPCIE=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_V4L_MEM2MEM_DRIVERS=y ++CONFIG_VIDEO_ROCKCHIP_RGA=m ++CONFIG_SMS_SDIO_DRV=m ++CONFIG_RADIO_SI470X=m ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_RADIO_SI4713=m ++CONFIG_USB_SI4713=m ++CONFIG_PLATFORM_SI4713=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_MAXIRADIO=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_RAREMONO=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_DRM=m ++CONFIG_DRM_LOAD_EDID_FIRMWARE=y ++CONFIG_DRM_I2C_NXP_TDA998X=m ++CONFIG_DRM_HDLCD=m ++CONFIG_DRM_MALI_DISPLAY=m ++CONFIG_DRM_RADEON=m ++CONFIG_DRM_RADEON_USERPTR=y ++CONFIG_DRM_AMDGPU=m ++CONFIG_DRM_NOUVEAU=m ++CONFIG_DRM_VGEM=m ++CONFIG_DRM_ROCKCHIP=m ++CONFIG_ROCKCHIP_ANALOGIX_DP=y ++CONFIG_ROCKCHIP_CDN_DP=y ++CONFIG_ROCKCHIP_DW_HDMI=y ++CONFIG_ROCKCHIP_DW_MIPI_DSI=y ++CONFIG_ROCKCHIP_INNO_HDMI=y ++CONFIG_ROCKCHIP_LVDS=y ++CONFIG_ROCKCHIP_RGB=y ++CONFIG_DRM_UDL=m ++CONFIG_DRM_AST=m ++CONFIG_DRM_MGAG200=m ++CONFIG_DRM_CIRRUS_QEMU=m ++CONFIG_DRM_QXL=m ++CONFIG_DRM_BOCHS=m ++CONFIG_DRM_VIRTIO_GPU=m ++CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m ++CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_NXP_PTN3460=m ++CONFIG_DRM_PARADE_PS8622=m ++CONFIG_DRM_SIL_SII8620=m ++CONFIG_DRM_SII902X=m ++CONFIG_DRM_TOSHIBA_TC358767=m ++CONFIG_DRM_TI_TFP410=m ++CONFIG_DRM_ANALOGIX_ANX78XX=m ++CONFIG_DRM_I2C_ADV7511=m ++CONFIG_DRM_I2C_ADV7511_AUDIO=y ++CONFIG_DRM_DW_HDMI_CEC=m ++CONFIG_DRM_HISI_KIRIN=m ++CONFIG_DRM_PL111=m ++CONFIG_DRM_PANFROST=m ++CONFIG_FB=y ++CONFIG_FIRMWARE_EDID=y ++CONFIG_FB_TILEBLITTING=y ++CONFIG_FB_UDL=m ++CONFIG_FB_VIRTUAL=m ++CONFIG_FB_SIMPLE=y ++CONFIG_FB_SSD1307=m ++CONFIG_LCD_CLASS_DEVICE=m ++CONFIG_LCD_PLATFORM=m ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_GENERIC=m ++CONFIG_BACKLIGHT_PWM=m ++CONFIG_BACKLIGHT_LP855X=m ++CONFIG_BACKLIGHT_GPIO=m ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y ++CONFIG_SOUND=y ++CONFIG_SND=y ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_HRTIMER=m ++# CONFIG_SND_SUPPORT_OLD_API is not set ++CONFIG_SND_VERBOSE_PRINTK=y ++CONFIG_SND_DEBUG=y ++CONFIG_SND_DEBUG_VERBOSE=y ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_SEQUENCER_OSS=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_AC97_POWER_SAVE=y ++CONFIG_SND_AD1889=m ++CONFIG_SND_ATIIXP=m ++CONFIG_SND_ATIIXP_MODEM=m ++CONFIG_SND_AU8810=m ++CONFIG_SND_AU8820=m ++CONFIG_SND_AU8830=m ++CONFIG_SND_BT87X=m ++CONFIG_SND_CA0106=m ++CONFIG_SND_CMIPCI=m ++CONFIG_SND_OXYGEN=m ++CONFIG_SND_CS4281=m ++CONFIG_SND_CS46XX=m ++CONFIG_SND_CTXFI=m ++CONFIG_SND_DARLA20=m ++CONFIG_SND_GINA20=m ++CONFIG_SND_LAYLA20=m ++CONFIG_SND_DARLA24=m ++CONFIG_SND_GINA24=m ++CONFIG_SND_LAYLA24=m ++CONFIG_SND_MONA=m ++CONFIG_SND_MIA=m ++CONFIG_SND_ECHO3G=m ++CONFIG_SND_INDIGO=m ++CONFIG_SND_INDIGOIO=m ++CONFIG_SND_INDIGODJ=m ++CONFIG_SND_INDIGOIOX=m ++CONFIG_SND_INDIGODJX=m ++CONFIG_SND_ENS1370=m ++CONFIG_SND_ENS1371=m ++CONFIG_SND_FM801=m ++CONFIG_SND_FM801_TEA575X_BOOL=y ++CONFIG_SND_HDSP=m ++CONFIG_SND_HDSPM=m ++CONFIG_SND_ICE1724=m ++CONFIG_SND_INTEL8X0=m ++CONFIG_SND_INTEL8X0M=m ++CONFIG_SND_KORG1212=m ++CONFIG_SND_LOLA=m ++CONFIG_SND_LX6464ES=m ++CONFIG_SND_MIXART=m ++CONFIG_SND_NM256=m ++CONFIG_SND_PCXHR=m ++CONFIG_SND_RIPTIDE=m ++CONFIG_SND_RME32=m ++CONFIG_SND_RME96=m ++CONFIG_SND_RME9652=m ++CONFIG_SND_VIA82XX=m ++CONFIG_SND_VIA82XX_MODEM=m ++CONFIG_SND_VIRTUOSO=m ++CONFIG_SND_VX222=m ++CONFIG_SND_YMFPCI=m ++CONFIG_SND_HDA_INTEL=m ++CONFIG_SND_HDA_HWDEP=y ++CONFIG_SND_HDA_INPUT_BEEP=y ++CONFIG_SND_HDA_INPUT_BEEP_MODE=0 ++CONFIG_SND_HDA_PATCH_LOADER=y ++CONFIG_SND_HDA_CODEC_REALTEK=m ++CONFIG_SND_HDA_CODEC_ANALOG=m ++CONFIG_SND_HDA_CODEC_SIGMATEL=m ++CONFIG_SND_HDA_CODEC_VIA=m ++CONFIG_SND_HDA_CODEC_HDMI=m ++CONFIG_SND_HDA_CODEC_CIRRUS=m ++CONFIG_SND_HDA_CODEC_CONEXANT=m ++CONFIG_SND_HDA_CODEC_CA0110=m ++CONFIG_SND_HDA_CODEC_CA0132=m ++CONFIG_SND_HDA_CODEC_CMEDIA=m ++CONFIG_SND_HDA_CODEC_SI3054=m ++CONFIG_SND_HDA_PREALLOC_SIZE=4096 ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_USB_HIFACE=m ++CONFIG_SND_USB_POD=m ++CONFIG_SND_USB_PODHD=m ++CONFIG_SND_USB_TONEPORT=m ++CONFIG_SND_USB_VARIAX=m ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AMD_ACP=m ++CONFIG_SND_I2S_HI6210_I2S=m ++CONFIG_SND_SOC_ROCKCHIP=m ++CONFIG_SND_SOC_ROCKCHIP_PDM=m ++CONFIG_SND_SOC_ROCKCHIP_SPDIF=m ++CONFIG_SND_SOC_ROCKCHIP_MAX98090=m ++CONFIG_SND_SOC_ROCKCHIP_RT5645=m ++CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m ++CONFIG_SND_SOC_RK3399_GRU_SOUND=m ++CONFIG_SND_SOC_CROS_EC_CODEC=m ++CONFIG_SND_SOC_ES8316=m ++CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y ++CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y ++CONFIG_SND_SOC_PCM3168A_I2C=m ++CONFIG_SND_SOC_RK3328=m ++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_SND_AUDIO_GRAPH_CARD=m ++CONFIG_HID_BATTERY_STRENGTH=y ++CONFIG_HIDRAW=y ++CONFIG_UHID=m ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACCUTOUCH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_ACRUX_FF=y ++CONFIG_HID_APPLE=m ++CONFIG_HID_APPLEIR=m ++CONFIG_HID_AUREAL=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_BETOP_FF=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CORSAIR=m ++CONFIG_HID_COUGAR=m ++CONFIG_HID_MACALLY=m ++CONFIG_HID_PRODIKEYS=m ++CONFIG_HID_CMEDIA=m ++CONFIG_HID_CP2112=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_DRAGONRISE_FF=y ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_GEMBIRD=m ++CONFIG_HID_GFRM=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HOLTEK_FF=y ++CONFIG_HID_GT683R=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_VIEWSONIC=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_ICADE=m ++CONFIG_HID_ITE=m ++CONFIG_HID_JABRA=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LENOVO=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_LOGITECH_DJ=m ++CONFIG_LOGITECH_FF=y ++CONFIG_LOGIRUMBLEPAD2_FF=y ++CONFIG_LOGIG940_FF=y ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MALTRON=m ++CONFIG_HID_MAYFLASH=m ++CONFIG_HID_REDRAGON=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTI=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_PANTHERLORD_FF=y ++CONFIG_HID_PENMOUNT=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_PICOLCD_FB=y ++CONFIG_HID_PICOLCD_BACKLIGHT=y ++CONFIG_HID_PICOLCD_LCD=y ++CONFIG_HID_PICOLCD_LEDS=y ++CONFIG_HID_PICOLCD_CIR=y ++CONFIG_HID_PLANTRONICS=m ++CONFIG_HID_PRIMAX=m ++CONFIG_HID_RETRODE=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAITEK=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_SONY_FF=y ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_STEAM=m ++CONFIG_HID_STEELSERIES=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_RMI=m ++CONFIG_HID_GREENASIA=m ++CONFIG_GREENASIA_FF=y ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_SMARTJOYPLUS_FF=y ++CONFIG_HID_TIVO=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_THRUSTMASTER_FF=y ++CONFIG_HID_UDRAW_PS3=m ++CONFIG_HID_U2FZERO=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_ZEROPLUS_FF=y ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_SENSOR_HUB=m ++CONFIG_HID_SENSOR_CUSTOM_SENSOR=m ++CONFIG_HID_ALPS=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_I2C_HID=m ++CONFIG_USB_LED_TRIG=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_OTG=y ++CONFIG_USB_MON=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_HCD_PLATFORM=y ++CONFIG_USB_MAX3421_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_HCD_PLATFORM=y ++CONFIG_USB_UHCI_HCD=y ++CONFIG_USB_U132_HCD=m ++CONFIG_USB_SL811_HCD=m ++CONFIG_USB_SL811_HCD_ISO=y ++CONFIG_USB_PRINTER=m ++CONFIG_USB_TMC=m ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=y ++CONFIG_USB_STORAGE_DATAFAB=y ++CONFIG_USB_STORAGE_FREECOM=y ++CONFIG_USB_STORAGE_ISD200=y ++CONFIG_USB_STORAGE_USBAT=y ++CONFIG_USB_STORAGE_SDDR09=y ++CONFIG_USB_STORAGE_SDDR55=y ++CONFIG_USB_STORAGE_JUMPSHOT=y ++CONFIG_USB_STORAGE_ALAUDA=y ++CONFIG_USB_STORAGE_ONETOUCH=y ++CONFIG_USB_STORAGE_KARMA=y ++CONFIG_USB_STORAGE_CYPRESS_ATACB=y ++CONFIG_USB_STORAGE_ENE_UB6250=y ++CONFIG_USB_UAS=y ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USBIP_VUDC=m ++CONFIG_USB_MUSB_HDRC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_ULPI=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC2_PCI=y ++CONFIG_USB_CHIPIDEA=y ++CONFIG_USB_CHIPIDEA_UDC=y ++CONFIG_USB_CHIPIDEA_HOST=y ++CONFIG_USB_ISP1760=y ++CONFIG_USB_SERIAL=y ++CONFIG_USB_SERIAL_CONSOLE=y ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_SIMPLE=m ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_F8153X=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_MXUPORT=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SAFE_PADDED=y ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_UPD78F0730=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_SISUSBVGA=m ++CONFIG_USB_SISUSBVGA_CON=y ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_HSIC_USB3503=y ++CONFIG_USB_HSIC_USB4604=y ++CONFIG_USB_CHAOSKEY=m ++CONFIG_USB_ATM=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m ++CONFIG_USB_GPIO_VBUS=y ++CONFIG_USB_ISP1301=y ++CONFIG_USB_ULPI=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VBUS_DRAW=500 ++CONFIG_USB_CONFIGFS=m ++CONFIG_USB_CONFIGFS_SERIAL=y ++CONFIG_USB_CONFIGFS_ACM=y ++CONFIG_USB_CONFIGFS_OBEX=y ++CONFIG_USB_CONFIGFS_NCM=y ++CONFIG_USB_CONFIGFS_ECM=y ++CONFIG_USB_CONFIGFS_ECM_SUBSET=y ++CONFIG_USB_CONFIGFS_RNDIS=y ++CONFIG_USB_CONFIGFS_EEM=y ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++CONFIG_USB_CONFIGFS_F_FS=y ++CONFIG_USB_CONFIGFS_F_UAC1=y ++CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y ++CONFIG_USB_CONFIGFS_F_UAC2=y ++CONFIG_USB_CONFIGFS_F_MIDI=y ++CONFIG_USB_CONFIGFS_F_HID=y ++CONFIG_USB_CONFIGFS_F_UVC=y ++CONFIG_USB_CONFIGFS_F_PRINTER=y ++CONFIG_USB_CONFIGFS_F_TCM=y ++CONFIG_USB_AUDIO=m ++CONFIG_GADGET_UAC1=y ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_EEM=y ++CONFIG_USB_G_NCM=m ++CONFIG_USB_GADGETFS=m ++CONFIG_USB_FUNCTIONFS=m ++CONFIG_USB_FUNCTIONFS_ETH=y ++CONFIG_USB_FUNCTIONFS_RNDIS=y ++CONFIG_USB_FUNCTIONFS_GENERIC=y ++CONFIG_USB_MASS_STORAGE=m ++CONFIG_USB_GADGET_TARGET=m ++CONFIG_USB_G_SERIAL=m ++CONFIG_USB_MIDI_GADGET=m ++CONFIG_USB_G_PRINTER=m ++CONFIG_USB_CDC_COMPOSITE=m ++CONFIG_USB_G_ACM_MS=m ++CONFIG_USB_G_MULTI=m ++CONFIG_USB_G_MULTI_CDC=y ++CONFIG_USB_G_HID=m ++CONFIG_USB_G_WEBCAM=m ++CONFIG_TYPEC=y ++CONFIG_TYPEC_TCPM=y ++CONFIG_TYPEC_TCPCI=y ++CONFIG_TYPEC_FUSB302=y ++CONFIG_TYPEC_DP_ALTMODE=y ++CONFIG_MMC=y ++CONFIG_PWRSEQ_SD8787=m ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_SDIO_UART=m ++CONFIG_MMC_ARMMMCI=y ++# CONFIG_MMC_STM32_SDMMC is not set ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PCI=y ++CONFIG_MMC_SDHCI_ACPI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_OF_ARASAN=y ++CONFIG_MMC_SDHCI_OF_AT91=y ++CONFIG_MMC_SDHCI_CADENCE=y ++CONFIG_MMC_SDHCI_F_SDH30=y ++CONFIG_MMC_TIFM_SD=y ++CONFIG_MMC_SPI=y ++CONFIG_MMC_CB710=y ++CONFIG_MMC_VIA_SDMMC=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_EXYNOS=y ++CONFIG_MMC_DW_K3=y ++CONFIG_MMC_DW_PCI=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_VUB300=m ++CONFIG_MMC_USHC=m ++CONFIG_MMC_USDHI6ROL0=y ++CONFIG_MMC_TOSHIBA_PCI=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SDHCI_XENON=y ++CONFIG_MEMSTICK=m ++CONFIG_MSPRO_BLOCK=m ++CONFIG_MEMSTICK_TIFM_MS=m ++CONFIG_MEMSTICK_JMICRON_38X=m ++CONFIG_MEMSTICK_R592=m ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_FLASH=m ++CONFIG_LEDS_LM3530=m ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_LP3944=m ++CONFIG_LEDS_PCA955X=m ++CONFIG_LEDS_PCA963X=m ++CONFIG_LEDS_PWM=m ++CONFIG_LEDS_LT3593=m ++CONFIG_LEDS_BLINKM=m ++CONFIG_LEDS_SYSCON=y ++CONFIG_LEDS_USER=m ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_DISK=y ++CONFIG_LEDS_TRIGGER_MTD=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_ACTIVITY=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=y ++CONFIG_LEDS_TRIGGER_CAMERA=y ++CONFIG_LEDS_TRIGGER_PANIC=y ++CONFIG_LEDS_TRIGGER_NETDEV=y ++CONFIG_LEDS_TRIGGER_PATTERN=m ++CONFIG_LEDS_TRIGGER_AUDIO=m ++CONFIG_ACCESSIBILITY=y ++CONFIG_A11Y_BRAILLE_CONSOLE=y ++CONFIG_EDAC=y ++CONFIG_EDAC_XGENE=m ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_SYSTOHC is not set ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++CONFIG_RTC_DRV_ABX80X=m ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1374_WDT=y ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RK808=y ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF85063=m ++CONFIG_RTC_DRV_PCF85363=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_M41T80_WDT=y ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_DS1286=m ++CONFIG_RTC_DRV_DS1511=m ++CONFIG_RTC_DRV_DS1553=m ++CONFIG_RTC_DRV_DS1685_FAMILY=m ++CONFIG_RTC_DRV_DS1742=m ++CONFIG_RTC_DRV_DS2404=m ++CONFIG_RTC_DRV_EFI=y ++CONFIG_RTC_DRV_STK17TA8=m ++CONFIG_RTC_DRV_M48T35=m ++CONFIG_RTC_DRV_M48T59=m ++CONFIG_RTC_DRV_MSM6242=m ++CONFIG_RTC_DRV_BQ4802=m ++CONFIG_RTC_DRV_RP5C01=m ++CONFIG_RTC_DRV_V3020=m ++CONFIG_RTC_DRV_CROS_EC=y ++CONFIG_RTC_DRV_PL031=y ++CONFIG_MV_XOR_V2=y ++CONFIG_PL330_DMA=y ++CONFIG_QCOM_HIDMA_MGMT=y ++CONFIG_QCOM_HIDMA=y ++CONFIG_DW_DMAC=m ++CONFIG_DW_DMAC_PCI=m ++CONFIG_ASYNC_TX_DMA=y ++CONFIG_AUXDISPLAY=y ++CONFIG_UIO_CIF=m ++CONFIG_UIO_AEC=m ++CONFIG_UIO_SERCOS3=m ++CONFIG_UIO_PCI_GENERIC=m ++CONFIG_VFIO=m ++CONFIG_VFIO_PCI=m ++CONFIG_VFIO_PLATFORM=m ++CONFIG_VFIO_AMBA=m ++CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m ++CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m ++CONFIG_VIRTIO_PCI=y ++CONFIG_VIRTIO_BALLOON=m ++CONFIG_VIRTIO_INPUT=m ++CONFIG_VIRTIO_MMIO=m ++CONFIG_VHOST_NET=m ++CONFIG_VHOST_SCSI=m ++CONFIG_VHOST_VSOCK=m ++CONFIG_STAGING=y ++CONFIG_PRISM2_USB=m ++CONFIG_RTL8192U=m ++CONFIG_RTLLIB=m ++CONFIG_RTL8192E=m ++CONFIG_R8712U=m ++CONFIG_R8188EU=m ++CONFIG_ADIS16203=m ++CONFIG_ADIS16240=m ++CONFIG_AD7816=m ++CONFIG_AD7280=m ++CONFIG_ADT7316=m ++CONFIG_ADT7316_I2C=m ++CONFIG_AD7150=m ++CONFIG_AD7746=m ++CONFIG_AD9832=m ++CONFIG_AD9834=m ++CONFIG_AD5933=m ++CONFIG_ADE7854=m ++CONFIG_AD2S1210=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_VIDEO_HANTRO=y ++CONFIG_VIDEO_USBVISION=m ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_HX8357D=m ++CONFIG_FB_TFT_ILI9163=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SH1106=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1305=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_ST7789V=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1611=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_FB_TFT_WATTEROTT=m ++CONFIG_MFD_CROS_EC=y ++CONFIG_CHROMEOS_TBMC=m ++CONFIG_CROS_EC_I2C=y ++CONFIG_CROS_EC_RPMSG=m ++CONFIG_CROS_EC_SPI=y ++CONFIG_CROS_KBD_LED_BACKLIGHT=y ++CONFIG_CROS_EC_LIGHTBAR=m ++CONFIG_CROS_EC_VBC=m ++CONFIG_CROS_EC_DEBUGFS=m ++CONFIG_CROS_EC_SYSFS=m ++CONFIG_COMMON_CLK_VERSATILE=y ++CONFIG_CLK_SP810=y ++CONFIG_CLK_VEXPRESS_OSC=y ++CONFIG_COMMON_CLK_RK808=y ++CONFIG_COMMON_CLK_SCPI=y ++CONFIG_COMMON_CLK_XGENE=y ++CONFIG_COMMON_CLK_PWM=y ++CONFIG_HWSPINLOCK=y ++CONFIG_ARM_MHU=y ++CONFIG_PLATFORM_MHU=y ++CONFIG_ROCKCHIP_MBOX=y ++CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y ++CONFIG_ROCKCHIP_IOMMU=y ++CONFIG_ARM_SMMU=y ++CONFIG_ARM_SMMU_V3=y ++CONFIG_REMOTEPROC=y ++CONFIG_RPMSG_CHAR=y ++CONFIG_RPMSG_QCOM_GLINK_RPM=y ++CONFIG_ROCKCHIP_PM_DOMAINS=y ++CONFIG_ROCKCHIP_SUSPEND_MODE=y ++CONFIG_DEVFREQ_GOV_PERFORMANCE=y ++CONFIG_ARM_RK3399_DMC_DEVFREQ=y ++CONFIG_EXTCON_ADC_JACK=m ++CONFIG_EXTCON_GPIO=y ++CONFIG_EXTCON_USB_GPIO=y ++CONFIG_EXTCON_USBC_CROS_EC=y ++CONFIG_MEMORY=y ++CONFIG_IIO=y ++CONFIG_IIO_BUFFER_CB=y ++CONFIG_IIO_BUFFER_HW_CONSUMER=m ++CONFIG_IIO_SW_DEVICE=m ++CONFIG_IIO_SW_TRIGGER=m ++CONFIG_ADIS16201=m ++CONFIG_ADIS16209=m ++CONFIG_ADXL345_I2C=m ++CONFIG_ADXL345_SPI=m ++CONFIG_ADXL372_SPI=m ++CONFIG_ADXL372_I2C=m ++CONFIG_BMA180=m ++CONFIG_BMA220=m ++CONFIG_BMC150_ACCEL=m ++CONFIG_DA280=m ++CONFIG_DA311=m ++CONFIG_DMARD06=m ++CONFIG_DMARD09=m ++CONFIG_DMARD10=m ++CONFIG_HID_SENSOR_ACCEL_3D=m ++CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m ++CONFIG_IIO_ST_ACCEL_3AXIS=m ++CONFIG_KXSD9=m ++CONFIG_KXCJK1013=m ++CONFIG_MC3230=m ++CONFIG_MMA7455_I2C=m ++CONFIG_MMA7455_SPI=m ++CONFIG_MMA7660=m ++CONFIG_MMA8452=m ++CONFIG_MMA9551=m ++CONFIG_MMA9553=m ++CONFIG_MXC4005=m ++CONFIG_MXC6255=m ++CONFIG_SCA3000=m ++CONFIG_STK8312=m ++CONFIG_STK8BA50=m ++CONFIG_AD7124=m ++CONFIG_AD7192=m ++CONFIG_AD7266=m ++CONFIG_AD7291=m ++CONFIG_AD7298=m ++CONFIG_AD7476=m ++CONFIG_AD7606_IFACE_PARALLEL=m ++CONFIG_AD7606_IFACE_SPI=m ++CONFIG_AD7766=m ++CONFIG_AD7768_1=m ++CONFIG_AD7780=m ++CONFIG_AD7791=m ++CONFIG_AD7793=m ++CONFIG_AD7887=m ++CONFIG_AD7923=m ++CONFIG_AD7949=m ++CONFIG_AD799X=m ++CONFIG_AXP20X_ADC=m ++CONFIG_AXP288_ADC=m ++CONFIG_CC10001_ADC=m ++CONFIG_ENVELOPE_DETECTOR=m ++CONFIG_HI8435=m ++CONFIG_HX711=m ++CONFIG_INA2XX_ADC=m ++CONFIG_LTC2471=m ++CONFIG_LTC2485=m ++CONFIG_LTC2497=m ++CONFIG_MAX1027=m ++CONFIG_MAX11100=m ++CONFIG_MAX1118=m ++CONFIG_MAX1363=m ++CONFIG_MAX9611=m ++CONFIG_MCP320X=m ++CONFIG_MCP3422=m ++CONFIG_MCP3911=m ++CONFIG_NAU7802=m ++CONFIG_QCOM_SPMI_IADC=m ++CONFIG_QCOM_SPMI_VADC=y ++CONFIG_QCOM_SPMI_ADC5=m ++CONFIG_ROCKCHIP_SARADC=m ++CONFIG_SD_ADC_MODULATOR=m ++CONFIG_TI_ADC081C=m ++CONFIG_TI_ADC0832=m ++CONFIG_TI_ADC084S021=m ++CONFIG_TI_ADC12138=m ++CONFIG_TI_ADC108S102=m ++CONFIG_TI_ADC128S052=m ++CONFIG_TI_ADC161S626=m ++CONFIG_TI_ADS1015=m ++CONFIG_TI_ADS7950=m ++CONFIG_TI_ADS8344=m ++CONFIG_TI_ADS8688=m ++CONFIG_TI_ADS124S08=m ++CONFIG_TI_TLC4541=m ++CONFIG_VF610_ADC=m ++CONFIG_VIPERBOARD_ADC=m ++CONFIG_IIO_RESCALE=m ++CONFIG_AD8366=m ++CONFIG_ATLAS_PH_SENSOR=m ++CONFIG_BME680=m ++CONFIG_CCS811=m ++CONFIG_IAQCORE=m ++CONFIG_PMS7003=m ++CONFIG_SENSIRION_SGP30=m ++CONFIG_SPS30=m ++CONFIG_VZ89X=m ++CONFIG_IIO_CROS_EC_SENSORS_CORE=m ++CONFIG_IIO_CROS_EC_SENSORS=m ++CONFIG_AD5064=m ++CONFIG_AD5360=m ++CONFIG_AD5380=m ++CONFIG_AD5421=m ++CONFIG_AD5446=m ++CONFIG_AD5449=m ++CONFIG_AD5592R=m ++CONFIG_AD5593R=m ++CONFIG_AD5504=m ++CONFIG_AD5624R_SPI=m ++CONFIG_AD5686_SPI=m ++CONFIG_AD5696_I2C=m ++CONFIG_AD5755=m ++CONFIG_AD5758=m ++CONFIG_AD5761=m ++CONFIG_AD5764=m ++CONFIG_AD5791=m ++CONFIG_AD7303=m ++CONFIG_AD8801=m ++CONFIG_DPOT_DAC=m ++CONFIG_DS4424=m ++CONFIG_LTC1660=m ++CONFIG_LTC2632=m ++CONFIG_M62332=m ++CONFIG_MAX517=m ++CONFIG_MAX5821=m ++CONFIG_MCP4725=m ++CONFIG_MCP4922=m ++CONFIG_TI_DAC082S085=m ++CONFIG_TI_DAC5571=m ++CONFIG_TI_DAC7311=m ++CONFIG_TI_DAC7612=m ++CONFIG_VF610_DAC=m ++CONFIG_AD9523=m ++CONFIG_ADF4350=m ++CONFIG_ADIS16080=m ++CONFIG_ADIS16130=m ++CONFIG_ADIS16136=m ++CONFIG_ADIS16260=m ++CONFIG_ADXRS450=m ++CONFIG_BMG160=m ++CONFIG_FXAS21002C=m ++CONFIG_HID_SENSOR_GYRO_3D=m ++CONFIG_MPU3050_I2C=m ++CONFIG_IIO_ST_GYRO_3AXIS=m ++CONFIG_ITG3200=m ++CONFIG_AFE4403=m ++CONFIG_AFE4404=m ++CONFIG_MAX30100=m ++CONFIG_MAX30102=m ++CONFIG_AM2315=m ++CONFIG_DHT11=m ++CONFIG_HDC100X=m ++CONFIG_HID_SENSOR_HUMIDITY=m ++CONFIG_HTS221=m ++CONFIG_HTU21=m ++CONFIG_SI7005=m ++CONFIG_SI7020=m ++CONFIG_ADIS16400=m ++CONFIG_ADIS16480=m ++CONFIG_BMI160_I2C=m ++CONFIG_BMI160_SPI=m ++CONFIG_KMX61=m ++CONFIG_INV_MPU6050_I2C=m ++CONFIG_INV_MPU6050_SPI=m ++CONFIG_IIO_ST_LSM6DSX=m ++CONFIG_ACPI_ALS=m ++CONFIG_ADJD_S311=m ++CONFIG_AL3320A=m ++CONFIG_APDS9300=m ++CONFIG_APDS9960=m ++CONFIG_BH1750=m ++CONFIG_BH1780=m ++CONFIG_CM32181=m ++CONFIG_CM3232=m ++CONFIG_CM3323=m ++CONFIG_CM3605=m ++CONFIG_CM36651=m ++CONFIG_IIO_CROS_EC_LIGHT_PROX=m ++CONFIG_GP2AP020A00F=m ++CONFIG_SENSORS_ISL29018=m ++CONFIG_SENSORS_ISL29028=m ++CONFIG_ISL29125=m ++CONFIG_HID_SENSOR_ALS=m ++CONFIG_HID_SENSOR_PROX=m ++CONFIG_JSA1212=m ++CONFIG_RPR0521=m ++CONFIG_LTR501=m ++CONFIG_LV0104CS=m ++CONFIG_MAX44000=m ++CONFIG_MAX44009=m ++CONFIG_OPT3001=m ++CONFIG_PA12203001=m ++CONFIG_SI1133=m ++CONFIG_SI1145=m ++CONFIG_STK3310=m ++CONFIG_ST_UVIS25=m ++CONFIG_TCS3414=m ++CONFIG_TCS3472=m ++CONFIG_SENSORS_TSL2563=m ++CONFIG_TSL2583=m ++CONFIG_TSL2772=m ++CONFIG_TSL4531=m ++CONFIG_US5182D=m ++CONFIG_VCNL4000=m ++CONFIG_VCNL4035=m ++CONFIG_VEML6070=m ++CONFIG_VL6180=m ++CONFIG_ZOPT2201=m ++CONFIG_AK8974=m ++CONFIG_AK09911=m ++CONFIG_BMC150_MAGN_I2C=m ++CONFIG_BMC150_MAGN_SPI=m ++CONFIG_MAG3110=m ++CONFIG_HID_SENSOR_MAGNETOMETER_3D=m ++CONFIG_MMC35240=m ++CONFIG_IIO_ST_MAGN_3AXIS=m ++CONFIG_SENSORS_HMC5843_I2C=m ++CONFIG_SENSORS_HMC5843_SPI=m ++CONFIG_SENSORS_RM3100_I2C=m ++CONFIG_SENSORS_RM3100_SPI=m ++CONFIG_IIO_MUX=y ++CONFIG_HID_SENSOR_INCLINOMETER_3D=m ++CONFIG_HID_SENSOR_DEVICE_ROTATION=m ++CONFIG_IIO_HRTIMER_TRIGGER=m ++CONFIG_IIO_INTERRUPT_TRIGGER=m ++CONFIG_IIO_TIGHTLOOP_TRIGGER=m ++CONFIG_IIO_SYSFS_TRIGGER=m ++CONFIG_AD5272=m ++CONFIG_DS1803=m ++CONFIG_MAX5481=m ++CONFIG_MAX5487=m ++CONFIG_MCP4018=m ++CONFIG_MCP4131=m ++CONFIG_MCP4531=m ++CONFIG_MCP41010=m ++CONFIG_TPL0102=m ++CONFIG_LMP91000=m ++CONFIG_ABP060MG=m ++CONFIG_BMP280=m ++CONFIG_IIO_CROS_EC_BARO=m ++CONFIG_HID_SENSOR_PRESS=m ++CONFIG_HP03=m ++CONFIG_MPL115_I2C=m ++CONFIG_MPL115_SPI=m ++CONFIG_MPL3115=m ++CONFIG_MS5611=m ++CONFIG_MS5611_I2C=m ++CONFIG_MS5611_SPI=m ++CONFIG_MS5637=m ++CONFIG_IIO_ST_PRESS=m ++CONFIG_T5403=m ++CONFIG_HP206C=m ++CONFIG_ZPA2326=m ++CONFIG_AS3935=m ++CONFIG_ISL29501=m ++CONFIG_LIDAR_LITE_V2=m ++CONFIG_MB1232=m ++CONFIG_RFD77402=m ++CONFIG_SRF04=m ++CONFIG_SX9500=m ++CONFIG_SRF08=m ++CONFIG_VL53L0X_I2C=m ++CONFIG_AD2S90=m ++CONFIG_AD2S1200=m ++CONFIG_MAXIM_THERMOCOUPLE=m ++CONFIG_HID_SENSOR_TEMP=m ++CONFIG_MLX90614=m ++CONFIG_MLX90632=m ++CONFIG_TMP006=m ++CONFIG_TMP007=m ++CONFIG_TSYS01=m ++CONFIG_TSYS02D=m ++CONFIG_MAX31856=m ++CONFIG_PWM_CROS_EC=m ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_PHY_XGENE=y ++CONFIG_PHY_QCOM_USB_HS=y ++CONFIG_PHY_QCOM_USB_HSIC=y ++CONFIG_PHY_ROCKCHIP_DP=y ++CONFIG_PHY_ROCKCHIP_EMMC=y ++CONFIG_PHY_ROCKCHIP_INNO_HDMI=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_PCIE=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_POWERCAP=y ++CONFIG_ARM_CCI_PMU=y ++CONFIG_ARM_CCN=y ++CONFIG_HISI_PMU=y ++CONFIG_LIBNVDIMM=y ++CONFIG_BLK_DEV_PMEM=m ++CONFIG_ND_BLK=m ++CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_MUX_GPIO=y ++CONFIG_VALIDATE_FS_PARSER=y ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_PROC_INFO=y ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_XFS_FS=y ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_GFS2_FS=m ++CONFIG_GFS2_FS_LOCKING_DLM=y ++CONFIG_OCFS2_FS=m ++# CONFIG_OCFS2_FS_STATS is not set ++# CONFIG_OCFS2_DEBUG_MASKLOG is not set ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y ++CONFIG_F2FS_FS_SECURITY=y ++CONFIG_FS_ENCRYPTION=y ++CONFIG_FANOTIFY=y ++CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y ++CONFIG_QUOTA_NETLINK_INTERFACE=y ++# CONFIG_PRINT_QUOTA_WARNING is not set ++CONFIG_QFMT_V2=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++CONFIG_CUSE=y ++CONFIG_OVERLAY_FS=m ++CONFIG_FSCACHE=m ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_OBJECT_LIST=y ++CONFIG_CACHEFILES=m ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=y ++CONFIG_NTFS_RW=y ++CONFIG_PROC_KCORE=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_HUGETLBFS=y ++CONFIG_EFIVAR_FS=y ++CONFIG_AFFS_FS=m ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_BEFS_FS=m ++CONFIG_UBIFS_FS=m ++CONFIG_CRAMFS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZ4=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_MINIX_FS=m ++CONFIG_ROMFS_FS=m ++CONFIG_PSTORE=y ++CONFIG_PSTORE_RAM=m ++CONFIG_SYSV_FS=m ++CONFIG_UFS_FS=m ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V2 is not set ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_NFS_V4_1=y ++CONFIG_NFS_V4_2=y ++# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_NFSD_BLOCKLAYOUT=y ++CONFIG_NFSD_SCSILAYOUT=y ++CONFIG_NFSD_FLEXFILELAYOUT=y ++CONFIG_NFSD_V4_SECURITY_LABEL=y ++CONFIG_SUNRPC_DEBUG=y ++CONFIG_CEPH_FS=m ++CONFIG_CEPH_FSCACHE=y ++CONFIG_CEPH_FS_POSIX_ACL=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_DFS_UPCALL=y ++CONFIG_CIFS_FSCACHE=y ++CONFIG_CODA_FS=m ++CONFIG_9P_FS=m ++CONFIG_9P_FSCACHE=y ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_9P_FS_SECURITY=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_NLS_MAC_ROMAN=m ++CONFIG_NLS_MAC_CELTIC=m ++CONFIG_NLS_MAC_CENTEURO=m ++CONFIG_NLS_MAC_CROATIAN=m ++CONFIG_NLS_MAC_CYRILLIC=m ++CONFIG_NLS_MAC_GAELIC=m ++CONFIG_NLS_MAC_GREEK=m ++CONFIG_NLS_MAC_ICELAND=m ++CONFIG_NLS_MAC_INUIT=m ++CONFIG_NLS_MAC_ROMANIAN=m ++CONFIG_NLS_MAC_TURKISH=m ++CONFIG_DLM=m ++CONFIG_DLM_DEBUG=y ++CONFIG_PERSISTENT_KEYRINGS=y ++CONFIG_BIG_KEYS=y ++CONFIG_TRUSTED_KEYS=m ++CONFIG_ENCRYPTED_KEYS=y ++CONFIG_SECURITY=y ++CONFIG_SECURITY_NETWORK=y ++CONFIG_SECURITY_NETWORK_XFRM=y ++CONFIG_SECURITY_YAMA=y ++# CONFIG_INTEGRITY is not set ++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" ++CONFIG_CRYPTO_USER=m ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set ++CONFIG_CRYPTO_PCRYPT=m ++CONFIG_CRYPTO_DH=m ++CONFIG_CRYPTO_AEGIS128=m ++CONFIG_CRYPTO_CFB=m ++CONFIG_CRYPTO_LRW=m ++CONFIG_CRYPTO_OFB=m ++CONFIG_CRYPTO_PCBC=m ++CONFIG_CRYPTO_KEYWRAP=m ++CONFIG_CRYPTO_ADIANTUM=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_VMAC=m ++CONFIG_CRYPTO_RMD128=m ++CONFIG_CRYPTO_RMD160=m ++CONFIG_CRYPTO_RMD256=m ++CONFIG_CRYPTO_RMD320=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_ANUBIS=m ++CONFIG_CRYPTO_BLOWFISH=m ++CONFIG_CRYPTO_CAMELLIA=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_CAST6=m ++CONFIG_CRYPTO_FCRYPT=m ++CONFIG_CRYPTO_KHAZAD=m ++CONFIG_CRYPTO_SALSA20=m ++CONFIG_CRYPTO_SEED=m ++CONFIG_CRYPTO_SERPENT=m ++CONFIG_CRYPTO_TEA=m ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_842=m ++CONFIG_CRYPTO_LZ4=m ++CONFIG_CRYPTO_LZ4HC=m ++CONFIG_CRYPTO_ANSI_CPRNG=m ++CONFIG_CRYPTO_DRBG_HASH=y ++CONFIG_CRYPTO_DRBG_CTR=y ++CONFIG_CRYPTO_USER_API_HASH=y ++CONFIG_CRYPTO_USER_API_SKCIPHER=y ++CONFIG_CRYPTO_USER_API_RNG=y ++CONFIG_CRYPTO_USER_API_AEAD=y ++CONFIG_CRYPTO_DEV_CCP=y ++CONFIG_CRYPTO_DEV_ROCKCHIP=m ++CONFIG_CRYPTO_DEV_SAFEXCEL=m ++CONFIG_CRYPTO_DEV_CCREE=m ++CONFIG_ASYMMETRIC_KEY_TYPE=y ++CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y ++CONFIG_X509_CERTIFICATE_PARSER=y ++CONFIG_PKCS7_MESSAGE_PARSER=y ++CONFIG_SYSTEM_TRUSTED_KEYRING=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=64 ++CONFIG_PRINTK_TIME=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DYNAMIC_DEBUG=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_STRIP_ASM_SYMS=y ++CONFIG_DEBUG_SECTION_MISMATCH=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 ++# CONFIG_MAGIC_SYSRQ_SERIAL is not set ++CONFIG_KGDB=y ++CONFIG_KGDB_TESTS=y ++CONFIG_DEBUG_VM=y ++CONFIG_SOFTLOCKUP_DETECTOR=y ++CONFIG_SCHEDSTATS=y ++CONFIG_STACKTRACE=y ++CONFIG_DEBUG_LIST=y ++CONFIG_RCU_TORTURE_TEST=m ++CONFIG_RCU_CPU_STALL_TIMEOUT=60 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_FTRACE is not set ++# CONFIG_RUNTIME_TESTING_MENU is not set +-- +2.25.4 + + +From a8f4db8a726e5e4552e61333dcd9ea1ff35f39f9 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm +Date: Sat, 6 Jun 2020 23:45:10 +0200 +Subject: [PATCH 25/25] arm64: dts: rockchip: setup USB type c port as dual + data role + +Some chargers try to put the charged device into device data role. +Before this commit this condition caused the tcpm state machine to +issue a hard reset due to a capability missmatch. + +Signed-off-by: Tobias Schramm +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index e2f83b556b6f..f3f5e953d7bf 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -726,7 +726,7 @@ fusb0: fusb30x@22 { + + connector { + compatible = "usb-c-connector"; +- data-role = "host"; ++ data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; +-- +2.25.4 +