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e5ea582133
Fix for https://github.com/NixOS/nixpkgs/issues/235179 Update Microchip uboot version to linux4microchip+fpga-2023.06 Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>
51 lines
2 KiB
Diff
51 lines
2 KiB
Diff
From 8afd811876b1ce8d6da6d5c804452a2b15805f5a Mon Sep 17 00:00:00 2001
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From: Ganga Ram <Ganga.Ram@tii.ae>
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Date: Wed, 5 Jul 2023 11:32:44 +0400
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Subject: [PATCH] From: Ganga Ram <Ganga.Ram@tii.ae> Date: Wed, 05 July 2023
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06:15:22 +0400 Subject: [PATCH] Riscv-Fix-build-against-binutils-2.38
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The following description is copied from the equivalent patch for the
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Linux Kernel proposed by Aurelien Jarno:
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From version 2.38, binutils default to ISA spec version 20191213. This
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means that the csr read/write (csrr*/csrw*) instructions and fence.i
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instruction has separated from the `I` extension, become two standalone
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extensions: Zicsr and Zifencei. As the kernel uses those instruction,
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this causes the following build failure:
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arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i', extension `zifencei' required
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arch/riscv/cpu/cpu.c:94: Error: unrecognized opcode `csrs sstatus,a5', extension `zicsr' required
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arch/riscv/cpu/cpu.c:95: Error: unrecognized opcode `csrw 0x003,0', extension `zicsr' required
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More detail: https://patchwork.ozlabs.org/series/283391/mbox/
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Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>
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---
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arch/riscv/Makefile | 11 ++++++++++-
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1 file changed, 10 insertions(+), 1 deletion(-)
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diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
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index 0b80eb8d86..53d1194ffb 100644
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--- a/arch/riscv/Makefile
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+++ b/arch/riscv/Makefile
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@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
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CMODEL = medany
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endif
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-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
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+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
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+
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+# Newer binutils versions default to ISA spec version 20191213 which moves some
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+# instructions from the I extension to the Zicsr and Zifencei extensions.
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+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
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+ifeq ($(toolchain-need-zicsr-zifencei),y)
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+ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
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+endif
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+
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+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
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-mcmodel=$(CMODEL)
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PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
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--
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2.39.2
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