157 lines
4 KiB
C
157 lines
4 KiB
C
/* Copyright (c) 2014, Cisco Systems, INC
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Written by XiangMingZhu WeiZhou MinPeng YanWang
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "cpu_support.h"
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#include "macros.h"
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#include "main.h"
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#include "pitch.h"
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#include "x86cpu.h"
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#if (defined(OPUS_X86_MAY_HAVE_SSE) && !defined(OPUS_X86_PRESUME_SSE)) || \
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(defined(OPUS_X86_MAY_HAVE_SSE2) && !defined(OPUS_X86_PRESUME_SSE2)) || \
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(defined(OPUS_X86_MAY_HAVE_SSE4_1) && !defined(OPUS_X86_PRESUME_SSE4_1)) || \
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(defined(OPUS_X86_MAY_HAVE_AVX) && !defined(OPUS_X86_PRESUME_AVX))
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#if defined(_MSC_VER)
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#include <intrin.h>
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static _inline void cpuid(unsigned int CPUInfo[4], unsigned int InfoType)
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{
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__cpuid((int*)CPUInfo, InfoType);
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}
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#else
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#if defined(CPU_INFO_BY_C)
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#include <cpuid.h>
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#endif
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static void cpuid(unsigned int CPUInfo[4], unsigned int InfoType)
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{
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#if defined(CPU_INFO_BY_ASM)
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#if defined(__i386__) && defined(__PIC__)
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/* %ebx is PIC register in 32-bit, so mustn't clobber it. */
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__asm__ __volatile__ (
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"xchg %%ebx, %1\n"
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"cpuid\n"
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"xchg %%ebx, %1\n":
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"=a" (CPUInfo[0]),
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"=r" (CPUInfo[1]),
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"=c" (CPUInfo[2]),
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"=d" (CPUInfo[3]) :
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"0" (InfoType)
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);
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#else
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__asm__ __volatile__ (
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"cpuid":
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"=a" (CPUInfo[0]),
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"=b" (CPUInfo[1]),
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"=c" (CPUInfo[2]),
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"=d" (CPUInfo[3]) :
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"0" (InfoType)
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);
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#endif
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#elif defined(CPU_INFO_BY_C)
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__get_cpuid(InfoType, &(CPUInfo[0]), &(CPUInfo[1]), &(CPUInfo[2]), &(CPUInfo[3]));
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#endif
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}
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#endif
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typedef struct CPU_Feature{
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/* SIMD: 128-bit */
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int HW_SSE;
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int HW_SSE2;
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int HW_SSE41;
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/* SIMD: 256-bit */
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int HW_AVX;
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} CPU_Feature;
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static void opus_cpu_feature_check(CPU_Feature *cpu_feature)
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{
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unsigned int info[4] = {0};
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unsigned int nIds = 0;
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cpuid(info, 0);
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nIds = info[0];
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if (nIds >= 1){
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cpuid(info, 1);
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cpu_feature->HW_SSE = (info[3] & (1 << 25)) != 0;
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cpu_feature->HW_SSE2 = (info[3] & (1 << 26)) != 0;
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cpu_feature->HW_SSE41 = (info[2] & (1 << 19)) != 0;
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cpu_feature->HW_AVX = (info[2] & (1 << 28)) != 0;
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}
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else {
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cpu_feature->HW_SSE = 0;
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cpu_feature->HW_SSE2 = 0;
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cpu_feature->HW_SSE41 = 0;
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cpu_feature->HW_AVX = 0;
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}
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}
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int opus_select_arch(void)
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{
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CPU_Feature cpu_feature;
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int arch;
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opus_cpu_feature_check(&cpu_feature);
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arch = 0;
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if (!cpu_feature.HW_SSE)
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{
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return arch;
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}
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arch++;
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if (!cpu_feature.HW_SSE2)
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{
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return arch;
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}
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arch++;
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if (!cpu_feature.HW_SSE41)
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{
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return arch;
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}
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arch++;
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if (!cpu_feature.HW_AVX)
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{
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return arch;
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}
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arch++;
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return arch;
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}
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#endif
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